| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | dc-glossary.rst | 37 * DISPCLK: Display Clock
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 44 double DISPCLK; member
281 double DISPCLK,
919 myPipe->DISPCLK, in CalculatePrefetchSchedule()
969 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) in CalculatePrefetchSchedule()
972 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK in CalculatePrefetchSchedule()
1870 // DISPCLK and DPPCLK Calculation in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1992 v->DISPCLK = v->DISPCLK_calculated; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2359 v->HTotal[k]) / v->DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2374 v->HTotal[k]) / v->DISPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2421 myPipe.DISPCLK in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3268 CalculateDynamicMetadataParameters(int MaxInterDCNTileRepeaters,double DPPCLK,double DISPCLK,double DCFClkDeepSleep,double PixelClock,unsigned int HTotal,unsigned int VBlank,unsigned int DynamicMetadataTransmittedBytes,int DynamicMetadataLinesBeforeActiveRequired,int InterlaceEnable,bool ProgressiveToInterlaceUnitInOPP,double * Tsetup,double * Tdmbf,double * Tdmec,double * Tdmsks) CalculateDynamicMetadataParameters() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_mode_vba_20v2.c | 65 double DISPCLK,
94 double DISPCLK,
472 double DISPCLK, in CalculateDelayAfterScaler() argument
520 if (DPPCLK == 0.0 || DISPCLK == 0.0) in CalculateDelayAfterScaler()
523 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK in CalculateDelayAfterScaler()
544 double DISPCLK, in CalculatePrefetchSchedule() argument
610 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); in CalculatePrefetchSchedule()
627 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; in CalculatePrefetchSchedule()
1152 // dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2026 / mode_lib->vba.DISPCLK; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| H A D | display_mode_vba_20.c | 59 double DISPCLK,
442 double DISPCLK, in CalculatePrefetchSchedule() argument
528 if (DPPCLK == 0.0 || DISPCLK == 0.0) in CalculatePrefetchSchedule()
531 *DSTXAfterScaler = DPPCycles * PixelClock / DPPCLK + DISPCLKCycles * PixelClock / DISPCLK in CalculatePrefetchSchedule()
547 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / DPPCLK + 3.0 / DISPCLK); in CalculatePrefetchSchedule()
564 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK; in CalculatePrefetchSchedule()
1092 // dml_ml->vba.DISPCLK and dml_ml->vba.DPPCLK Calculation in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1990 / mode_lib->vba.DISPCLK; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2009 / mode_lib->vba.DISPCLK); in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2091 mode_lib->vba.DISPCLK, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| H A D | dcn20_fpu.c | 1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 62 double DISPCLK; member
284 double DISPCLK,
946 myPipe->DISPCLK,
1009 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
1012 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
1019 dml_print("DML::%s: DISPCLK: %f\n", __func__, myPipe->DISPCLK);
2038 // DISPCLK and DPPCLK Calculation
2147 v->DISPCLK = v->DISPCLK_calculated;
2532 v->HTotal[k]) / v->DISPCLK;
3511 CalculateVupdateAndDynamicMetadataParameters(int MaxInterDCNTileRepeaters,double DPPCLK,double DISPCLK,double DCFClkDeepSleep,double PixelClock,int HTotal,int VBlank,int DynamicMetadataTransmittedBytes,int DynamicMetadataLinesBeforeActiveRequired,int InterlaceEnable,bool ProgressiveToInterlaceUnitInOPP,double * TSetup,double * Tdmbf,double * Tdmec,double * Tdmsks,int * VUpdateOffsetPix,double * VUpdateWidthPix,double * VReadyOffsetPix) global() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 64 double DISPCLK; member
275 double DISPCLK,
928 myPipe->DISPCLK,
991 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
994 *DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
1001 dml_print("DML::%s: DISPCLK: %f\n", __func__, myPipe->DISPCLK);
2020 // DISPCLK and DPPCLK Calculation
2129 v->DISPCLK = v->DISPCLK_calculated;
2513 v->HTotal[k]) / v->DISPCLK;
3405 CalculateVupdateAndDynamicMetadataParameters(int MaxInterDCNTileRepeaters,double DPPCLK,double DISPCLK,double DCFClkDeepSleep,double PixelClock,int HTotal,int VBlank,int DynamicMetadataTransmittedBytes,int DynamicMetadataLinesBeforeActiveRequired,int InterlaceEnable,bool ProgressiveToInterlaceUnitInOPP,double * TSetup,double * Tdmbf,double * Tdmec,double * Tdmsks,int * VUpdateOffsetPix,double * VUpdateWidthPix,double * VReadyOffsetPix) global() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_mode_vba_21.c | 43 double DISPCLK; member
737 if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) in CalculatePrefetchSchedule()
741 + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay; in CalculatePrefetchSchedule()
756 TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2.0 / myPipe->DPPCLK + 3.0 / myPipe->DISPCLK); in CalculatePrefetchSchedule()
773 Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / myPipe->DISPCLK; in CalculatePrefetchSchedule()
1476 // DISPCLK and DPPCLK Calculation in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2052 / mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2071 / mode_lib->vba.DISPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2138 myPipe.DISPCLK = mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 1096 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz; in ModeSupportAndSystemConfiguration()
1098 mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_vba.h | 436 double DISPCLK; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_32.c | 84 // DISPCLK and DPPCLK Calculation in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
611 mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
628 mode_lib->vba.HTotal[k]) / mode_lib->vba.DISPCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
764 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.Dispclk = mode_lib->vba.DISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2226 //DISPCLK/DPPCLK in dml32_ModeSupportAndSystemConfigurationFull()
3737 mode_lib->vba.DISPCLK = mode_lib->vba.RequiredDISPCLK[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; in dml32_ModeSupportAndSystemConfigurationFull()
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| H A D | dcn32_fpu.c | 1659 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn32_calculate_dlg_params()
2696 * Do it for DCFCLK, DISPCLK, DTBCLK and UCLK as any of those being in dcn32_patch_dpm_table()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | sienna_cichlid_ppt.c | 176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
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| H A D | navi10_ppt.c | 159 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
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