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Searched refs:umc (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/ !
H A Damdgpu_umc.c60 kcalloc(adev->umc.max_ras_err_cnt_per_query, in amdgpu_umc_page_retirement_mca()
64 "Failed to alloc memory for umc error record in MCA notifier!\n"); in amdgpu_umc_page_retirement_mca()
69 err_data.err_addr_len = adev->umc.max_ras_err_cnt_per_query; in amdgpu_umc_page_retirement_mca()
109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
110 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
111 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_handle_bad_pages()
113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
114 adev->umc in amdgpu_umc_handle_bad_pages()
540 amdgpu_umc_mca_to_addr(struct amdgpu_device * adev,uint64_t err_addr,uint32_t ch,uint32_t umc,uint32_t node,uint32_t socket,struct ta_ras_query_address_output * addr_out,bool dump_addr) amdgpu_umc_mca_to_addr() argument
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H A Dumc_v8_10.c27 #include "umc/umc_8_10_0_offset.h"
28 #include "umc/umc_8_10_0_sh_mask.h"
75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + in get_umc_v8_10_reg_offset()
216 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * in umc_v8_10_convert_error_address()
217 adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
218 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
234 dev_err(adev->dev, "Failed to map pa from umc na.\n"); in umc_v8_10_convert_error_address()
263 /* clear umc status */ in umc_v8_10_query_error_address()
281 /* clear umc statu in umc_v8_10_query_error_address()
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H A Dgmc_v9_0.c46 #include "umc/umc_6_0_sh_mask.h"
1413 adev->umc.funcs = &umc_v6_0_funcs; in gmc_v9_0_set_umc_funcs()
1416 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; in gmc_v9_0_set_umc_funcs()
1417 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1418 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; in gmc_v9_0_set_umc_funcs()
1419 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20; in gmc_v9_0_set_umc_funcs()
1420 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()
1421 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; in gmc_v9_0_set_umc_funcs()
1422 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1425 adev->umc in gmc_v9_0_set_umc_funcs()
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H A Damdgpu_umc.h45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
46 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
60 * v1 (legacy way): store channel index within a umc instance in eeprom
125 /* number of umc channel instance with memory map register access */
127 /* number of umc instance with memory map register access */
130 /* Total number of umc node instance including harvest one */
144 /* active mask for umc node instance */
189 uint64_t err_addr, uint32_t ch, uint32_t umc,
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H A Dumc_v12_0.c27 #include "umc/umc_12_0_0_offset.h"
28 #include "umc/umc_12_0_0_sh_mask.h"
39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v12_0_reg_offset()
45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + in get_umc_v12_0_reg_offset()
144 /* NOTE: node_inst is converted by adev->umc.active_mask and the range is [0-3], in umc_v12_0_query_error_count()
181 struct amdgpu_umc_flip_bits *flip_bits = &(adev->umc.flip_bits); in umc_v12_0_get_retire_flip_bits()
232 adev->umc.retire_unit = 0x1 << flip_bits->bit_num; in umc_v12_0_get_retire_flip_bits()
267 /* no need to care about umc inst if addr_in is NULL */ in umc_v12_0_convert_error_address()
271 flip_bits = adev->umc.flip_bits.flip_bits_in_pa; in umc_v12_0_convert_error_address()
272 bit_num = adev->umc in umc_v12_0_convert_error_address()
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H A Dgmc_v11_0.c545 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
546 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
547 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); in gmc_v11_0_set_umc_funcs()
548 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; in gmc_v11_0_set_umc_funcs()
549 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; in gmc_v11_0_set_umc_funcs()
550 if (adev->umc.node_inst_num == 4) in gmc_v11_0_set_umc_funcs()
551 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; in gmc_v11_0_set_umc_funcs()
553 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; in gmc_v11_0_set_umc_funcs()
554 adev->umc.ras = &umc_v8_10_ras; in gmc_v11_0_set_umc_funcs()
936 if (adev->umc in gmc_v11_0_hw_init()
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H A Dumc_v8_7.c30 #include "umc/umc_8_7_0_offset.h"
31 #include "umc/umc_8_7_0_sh_mask.h"
47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_v8_7_reg_offset()
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_correctable_error_count()
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v8_7_convert_error_address()
121 /* translate umc channel address to soc pa, 3 parts are included */ in umc_v8_7_convert_error_address()
139 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_error_address()
345 /* clear umc statu in umc_v8_7_query_error_address()
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H A Damdgpu_ras.c61 "umc",
445 * The block is one of: umc, sdma, gfx, etc.
461 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
462 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
463 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
471 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
526 /* umc ce/ue error injection for a bad page is not allowed */ in amdgpu_ras_debugfs_ctrl_write()
1030 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1031 adev->umc in amdgpu_ras_get_ecc_info()
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H A Dgmc_v10_0.c582 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; in gmc_v10_0_set_umc_funcs()
583 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
584 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
585 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; in gmc_v10_0_set_umc_funcs()
586 adev->umc.retire_unit = 1; in gmc_v10_0_set_umc_funcs()
587 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; in gmc_v10_0_set_umc_funcs()
588 adev->umc.ras = &umc_v8_7_ras; in gmc_v10_0_set_umc_funcs()
1011 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v10_0_hw_init()
1012 adev->umc in gmc_v10_0_hw_init()
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H A Dgmc_v12_0.c562 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; in gmc_v12_0_set_umc_funcs()
563 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); in gmc_v12_0_set_umc_funcs()
564 adev->umc.node_inst_num = 0; in gmc_v12_0_set_umc_funcs()
565 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); in gmc_v12_0_set_umc_funcs()
566 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; in gmc_v12_0_set_umc_funcs()
567 adev->umc.ras = &umc_v8_14_ras; in gmc_v12_0_set_umc_funcs()
904 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v12_0_hw_init()
905 adev->umc.funcs->init_registers(adev); in gmc_v12_0_hw_init()
H A Dumc_v8_14.h29 /* number of umc channel instance with memory map register access */
31 /* number of umc instance with memory map register access */
32 #define UMC_V8_14_UMC_INSTANCE_NUM(adev) ((adev)->umc.node_inst_num)
34 /* Total channel instances for all available umc nodes */
45 /* umc ce interrupt threshold */
47 /* umc ce count initial value */
H A Dumc_v6_1.c30 #include "umc/umc_6_1_1_offset.h"
31 #include "umc/umc_6_1_1_sh_mask.h"
32 #include "umc/umc_6_1_2_offset.h"
91 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; in get_umc_6_reg_offset()
303 uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_1_query_error_address()
325 /* clear umc status */ in umc_v6_1_query_error_address()
340 /* translate umc channel address to soc pa, 3 parts are included */ in umc_v6_1_query_error_address()
349 /* clear umc status */ in umc_v6_1_query_error_address()
H A Dumc_v8_14.c27 #include "umc/umc_8_14_0_offset.h"
28 #include "umc/umc_8_14_0_sh_mask.h"
34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
H A Damdgpu_discovery.c774 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & in amdgpu_discovery_read_from_harvest_table()
1436 adev->umc.node_inst_num++; in amdgpu_discovery_reg_base_init()
H A Damdgpu.h1145 struct amdgpu_umc umc; member
H A Damdgpu_psp.c1986 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; in psp_ras_initialize()
/linux/drivers/edac/ !
H A Damd64_edac.c1085 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1091 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1283 static int umc_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc, in umc_addr_mask_to_cs_size() argument
1326 addr_mask = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1329 addr_mask_sec = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1357 struct amd64_umc *umc; in umc_dump_misc_regs() local
1361 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1363 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in umc_dump_misc_regs()
1364 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc in umc_dump_misc_regs()
1439 int umc; umc_prep_chip_selects() local
1455 int cs, umc; umc_read_base_mask() local
1555 struct amd64_umc *umc; umc_determine_memory_type() local
2920 struct amd64_umc *umc; umc_read_mc_regs() local
3089 u8 umc, cs; umc_init_csrows() local
3376 struct amd64_umc *umc; umc_ecc_enabled() local
3526 gpu_addr_mask_to_cs_size(struct amd64_pvt * pvt,u8 umc,unsigned int cs_mode,int csrow_nr) gpu_addr_mask_to_cs_size() argument
3551 struct amd64_umc *umc; gpu_dump_misc_regs() local
3584 u8 umc, cs; gpu_init_csrows() local
3627 gpu_get_umc_base(struct amd64_pvt * pvt,u8 umc,u8 channel) gpu_get_umc_base() argument
3655 struct amd64_umc *umc; gpu_read_mc_regs() local
3678 int umc, cs; gpu_read_base_mask() local
3703 int umc; gpu_prep_chip_selects() local
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H A Damd64_edac.h382 struct amd64_umc *umc; /* UMC registers */ member
/linux/drivers/ras/amd/atl/ !
H A DMakefile16 amd_atl-y += umc.o
/linux/arch/x86/kernel/cpu/ !
H A DMakefile48 obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
/linux/drivers/scsi/ !
H A Dmegaraid.c3500 megacmd_t __user *umc; in mega_n_to_m() local
3520 umc = MBOX_P(uiocp); in mega_n_to_m()
3522 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()
3537 umc = (megacmd_t __user *)uioc_mimd->mbox; in mega_n_to_m()
3539 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()