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Searched refs:slice_bpg_offset (Results 1 – 8 of 8) sorted by relevance

/linux/include/drm/display/
H A Ddrm_dsc.h213 * @slice_bpg_offset: BPG offset used to enforce slice bit
215 u16 slice_bpg_offset; member
433 * @slice_bpg_offset:
437 __be16 slice_bpg_offset; member
/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Drc_calc_dpi.c63 to->slice_bpg_offset = from->slice_bpg_offset; in copy_pps_fields()
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c202 pps_payload->slice_bpg_offset = in drm_dsc_pps_payload_pack()
203 cpu_to_be16(dsc_cfg->slice_bpg_offset); in drm_dsc_pps_payload_pack()
1397 /* slice_bpg_offset is 16 bit value with 11 fractional bits */ in drm_dsc_compute_rc_parameters()
1398 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()
1413 vdsc_cfg->slice_bpg_offset) * in drm_dsc_compute_rc_parameters()
1500 cfg->initial_offset, cfg->final_offset, cfg->slice_bpg_offset); in drm_dsc_dump_config_main_params()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.c104 data |= dsc->slice_bpg_offset; in dpu_hw_dsc_config()
H A Ddpu_hw_dsc_1_2.c189 ((dsc->slice_bpg_offset & 0xffff) << 16); in dpu_hw_dsc_config_1_2()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c307 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); in dsc_log_pps()
546 reg_vals->pps.slice_bpg_offset = 0; in dsc_init_reg_values()
664 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); in dsc_write_to_registers()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c286 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); in dsc_write_to_registers()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.c5404 PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset); in intel_pipe_config_compare()