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Searched refs:sh_num (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc24.c137 u32 sh_num, in soc24_read_indexed_register() argument
143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc24_read_indexed_register()
144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc24_read_indexed_register()
148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc24_read_indexed_register()
156 u32 sh_num, u32 reg_offset) in soc24_get_register_value() argument
159 return soc24_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc24_get_register_value()
169 u32 sh_num, u32 reg_offset, u32 *value) in soc24_read_register() argument
185 se_num, sh_num, reg_offset); in soc24_read_register()
H A Dsoc21.c273 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register() argument
278 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
279 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
283 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
291 u32 sh_num, u32 reg_offset) in soc21_get_register_value() argument
294 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
303 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register() argument
319 se_num, sh_num, reg_offset); in soc21_read_register()
H A Dnv.c358 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
363 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in nv_read_indexed_register()
368 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
376 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
388 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
404 se_num, sh_num, reg_offset); in nv_read_register()
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dcik.c1124 u32 sh_num, u32 reg_offset) in cik_get_register_value() argument
1129 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1219 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register() argument
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
H A Dvi.c747 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
752 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
766 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
767 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in vi_get_register_value()
771 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
842 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
853 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
H A Dsi.c1180 u32 sh_num, u32 reg_offset) in si_get_register_value() argument
1185 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1197 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1198 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in si_get_register_value()
1202 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1254 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register() argument
1265 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
H A Dgfx_v9_4.c93 u32 sh_num, u32 instance) in gfx_v9_4_select_se_sh() argument
110 if (sh_num == 0xffffffff) in gfx_v9_4_select_se_sh()
114 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
H A Damdgpu_kms.c839 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
856 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { in amdgpu_info_ioctl()
857 sh_num = 0xffffffff; in amdgpu_info_ioctl()
858 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { in amdgpu_info_ioctl()
878 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Damdgpu_gfx.h337 u32 sh_num, u32 instance, int xcc_id);
H A Dgfx_v9_4_2.c848 u32 sh_num, u32 instance) in gfx_v9_4_2_select_se_sh() argument
865 if (sh_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
869 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
H A Dgfx_v6_0.c1305 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
1314 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1319 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1320 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1324 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
H A Dgfx_v7_0.c1552 * @sh_num: sh block to address
1559 u32 se_num, u32 sh_num, u32 instance, in gfx_v7_0_select_se_sh() argument
1569 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1574 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1575 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1579 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
H A Dgfx_v12_0.c278 u32 sh_num, u32 instance, int xcc_id);
1663 u32 sh_num, u32 instance, int xcc_id) in gfx_v12_0_select_se_sh() argument
1680 if (sh_num == 0xffffffff) in gfx_v12_0_select_se_sh()
1684 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_0_select_se_sh()
H A Damdgpu.h661 u32 sh_num, u32 reg_offset, u32 *value);
H A Dgfx_v9_4_3.c690 u32 sh_num, u32 instance, int xcc_id) in gfx_v9_4_3_xcc_select_se_sh() argument
707 if (sh_num == 0xffffffff) in gfx_v9_4_3_xcc_select_se_sh()
711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_3_xcc_select_se_sh()
H A Dgfx_v8_0.c3384 u32 se_num, u32 sh_num, u32 instance, in gfx_v8_0_select_se_sh() argument
3399 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3402 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
H A Dgfx_v9_0.c2499 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2514 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
/linux/drivers/gpu/drm/radeon/
H A Dsi.c2928 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2932 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2935 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in si_select_se_sh()
2936 else if (sh_num == 0xffffffff) in si_select_se_sh()
2939 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()