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Searched refs:ref_clk (Results 1 – 25 of 121) sorted by relevance

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/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns-usb2.c23 struct clk *ref_clk; member
36 err = clk_prepare_enable(usb2->ref_clk); in bcm_ns_usb2_phy_init()
42 ref_clk_rate = clk_get_rate(usb2->ref_clk); in bcm_ns_usb2_phy_init()
75 clk_disable_unprepare(usb2->ref_clk); in bcm_ns_usb2_phy_init()
109 usb2->ref_clk = devm_clk_get(dev, "phy-ref-clk"); in bcm_ns_usb2_probe()
110 if (IS_ERR(usb2->ref_clk)) { in bcm_ns_usb2_probe()
111 dev_err_probe(dev, PTR_ERR(usb2->ref_clk), "failed to get ref clk\n"); in bcm_ns_usb2_probe()
112 return PTR_ERR(usb2->ref_clk); in bcm_ns_usb2_probe()
/linux/drivers/phy/hisilicon/
H A Dphy-hisi-inno-usb2.c52 struct clk *ref_clk; member
100 ret = clk_prepare_enable(priv->ref_clk); in hisi_inno_phy_init()
124 clk_disable_unprepare(priv->ref_clk); in hisi_inno_phy_exit()
154 priv->ref_clk = devm_clk_get(dev, NULL); in hisi_inno_phy_probe()
155 if (IS_ERR(priv->ref_clk)) in hisi_inno_phy_probe()
156 return PTR_ERR(priv->ref_clk); in hisi_inno_phy_probe()
H A Dphy-histb-combphy.c48 struct clk *ref_clk; member
121 ret = clk_prepare_enable(priv->ref_clk); in histb_combphy_init()
154 clk_disable_unprepare(priv->ref_clk); in histb_combphy_exit()
244 priv->ref_clk = devm_clk_get(dev, NULL); in histb_combphy_probe()
245 if (IS_ERR(priv->ref_clk)) { in histb_combphy_probe()
247 return PTR_ERR(priv->ref_clk); in histb_combphy_probe()
/linux/drivers/clk/imx/
H A Dclk-pllv2.c81 long mfi, mfn, mfd, pdf, ref_clk; in __clk_pllv2_recalc_rate() local
94 ref_clk = 2 * parent_rate; in __clk_pllv2_recalc_rate()
96 ref_clk *= 2; in __clk_pllv2_recalc_rate()
98 ref_clk /= (pdf + 1); in __clk_pllv2_recalc_rate()
99 temp = (u64) ref_clk * abs(mfn); in __clk_pllv2_recalc_rate()
102 temp = (ref_clk * mfi) - temp; in __clk_pllv2_recalc_rate()
104 temp = (ref_clk * mfi) + temp; in __clk_pllv2_recalc_rate()
/linux/drivers/phy/samsung/
H A Dphy-samsung-usb2.c36 ret = clk_prepare_enable(drv->ref_clk); in samsung_usb2_phy_power_on()
50 clk_disable_unprepare(drv->ref_clk); in samsung_usb2_phy_power_on()
75 clk_disable_unprepare(drv->ref_clk); in samsung_usb2_phy_power_off()
199 drv->ref_clk = devm_clk_get(dev, "ref"); in samsung_usb2_phy_probe()
200 if (IS_ERR(drv->ref_clk)) { in samsung_usb2_phy_probe()
202 return PTR_ERR(drv->ref_clk); in samsung_usb2_phy_probe()
205 drv->ref_rate = clk_get_rate(drv->ref_clk); in samsung_usb2_phy_probe()
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_phy_8996.c103 static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk, in pll_get_cpctrl() argument
107 return (11000000 / (ref_clk / 20)); in pll_get_cpctrl()
128 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
135 base = (64 * ref_clk) / HDMI_DEFAULT_REF_CLOCK; in pll_get_integloop_gain()
137 base = (1022 * ref_clk) / 100; in pll_get_integloop_gain()
144 static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk) in pll_get_pll_cmp() argument
147 u32 divisor = ref_clk * 10; in pll_get_pll_cmp()
157 static inline u64 pll_cmp_to_fdata(u32 pll_cmp, unsigned long ref_clk) in pll_cmp_to_fdata() argument
159 u64 fdata = ((u64)pll_cmp) * ref_clk * 10; in pll_cmp_to_fdata()
218 static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk, in pll_calculate() argument
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H A Dhdmi_phy_8998.c102 static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk, in pll_get_cpctrl() argument
127 static inline u32 pll_get_integloop_gain(u64 frac_start, u64 bclk, u32 ref_clk, in pll_get_integloop_gain() argument
143 static inline u32 pll_get_pll_cmp(u64 fdata, unsigned long ref_clk) in pll_get_pll_cmp() argument
146 u32 divisor = ref_clk * 10; in pll_get_pll_cmp()
282 static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk, in pll_calculate() argument
307 pll_divisor = 4 * ref_clk; in pll_calculate()
317 cpctrl = pll_get_cpctrl(frac_start, ref_clk, false); in pll_calculate()
321 ref_clk, false); in pll_calculate()
326 pll_cmp = pll_get_pll_cmp(fdata, ref_clk); in pll_calculate()
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi.c110 struct clk *ref_clk; in mtk_mipi_tx_probe() local
132 ref_clk = devm_clk_get(dev, NULL); in mtk_mipi_tx_probe()
133 if (IS_ERR(ref_clk)) in mtk_mipi_tx_probe()
134 return dev_err_probe(dev, PTR_ERR(ref_clk), in mtk_mipi_tx_probe()
151 ref_clk_name = __clk_get_name(ref_clk); in mtk_mipi_tx_probe()
H A Dphy-mtk-hdmi.c104 struct clk *ref_clk; in mtk_hdmi_phy_probe() local
123 ref_clk = devm_clk_get(dev, "pll_ref"); in mtk_hdmi_phy_probe()
124 if (IS_ERR(ref_clk)) in mtk_hdmi_phy_probe()
125 return dev_err_probe(dev, PTR_ERR(ref_clk), in mtk_hdmi_phy_probe()
128 ref_clk_name = __clk_get_name(ref_clk); in mtk_hdmi_phy_probe()
H A Dphy-mtk-xsphy.c96 struct clk *ref_clk; /* reference clock of anolog phy */ member
386 ret = clk_prepare_enable(inst->ref_clk); in mtk_phy_init()
388 dev_err(xsphy->dev, "failed to enable ref_clk\n"); in mtk_phy_init()
406 clk_disable_unprepare(inst->ref_clk); in mtk_phy_init()
441 clk_disable_unprepare(inst->ref_clk); in mtk_phy_exit()
587 inst->ref_clk = devm_clk_get(&phy->dev, "ref"); in mtk_xsphy_probe()
588 if (IS_ERR(inst->ref_clk)) { in mtk_xsphy_probe()
589 dev_err(dev, "failed to get ref_clk(id-%d)\n", port); in mtk_xsphy_probe()
590 return PTR_ERR(inst->ref_clk); in mtk_xsphy_probe()
/linux/drivers/rtc/
H A Drtc-cadence.c82 struct clk *ref_clk; member
281 crtc->ref_clk = devm_clk_get(&pdev->dev, "ref_clk"); in cdns_rtc_probe()
282 if (IS_ERR(crtc->ref_clk)) { in cdns_rtc_probe()
283 ret = PTR_ERR(crtc->ref_clk); in cdns_rtc_probe()
302 ret = clk_prepare_enable(crtc->ref_clk); in cdns_rtc_probe()
309 ref_clk_freq = clk_get_rate(crtc->ref_clk); in cdns_rtc_probe()
349 clk_disable_unprepare(crtc->ref_clk); in cdns_rtc_probe()
365 clk_disable_unprepare(crtc->ref_clk); in cdns_rtc_remove()
/linux/drivers/gpu/drm/rockchip/
H A Ddw_hdmi-rockchip.c80 struct clk *ref_clk; member
210 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
211 if (!hdmi->ref_clk) in rockchip_hdmi_parse_dt()
212 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
214 if (IS_ERR(hdmi->ref_clk)) { in rockchip_hdmi_parse_dt()
215 ret = PTR_ERR(hdmi->ref_clk); in rockchip_hdmi_parse_dt()
246 if (hdmi->ref_clk) { in dw_hdmi_rockchip_mode_valid()
247 int rpclk = clk_round_rate(hdmi->ref_clk, pclk); in dw_hdmi_rockchip_mode_valid()
281 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); in dw_hdmi_rockchip_encoder_mode_set()
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-rx.c65 struct clk *ref_clk; member
123 clk_set_rate(dphy->ref_clk, 49500000); in stf_dphy_power_on()
171 dphy->ref_clk = devm_clk_get(&pdev->dev, "ref"); in stf_dphy_probe()
172 if (IS_ERR(dphy->ref_clk)) in stf_dphy_probe()
173 return PTR_ERR(dphy->ref_clk); in stf_dphy_probe()
/linux/drivers/clk/
H A Dclk-moxart.c20 struct clk *ref_clk; in moxart_of_pll_clk_init() local
37 ref_clk = of_clk_get(node, 0); in moxart_of_pll_clk_init()
38 if (IS_ERR(ref_clk)) { in moxart_of_pll_clk_init()
H A Dclk-cs2000-cp.c106 struct clk *ref_clk; member
442 struct clk *clk_in, *ref_clk; in cs2000_clk_get() local
449 ref_clk = devm_clk_get(dev, "ref_clk"); in cs2000_clk_get()
451 if (IS_ERR(ref_clk)) in cs2000_clk_get()
455 priv->ref_clk = ref_clk; in cs2000_clk_get()
486 ref_clk_rate = clk_get_rate(priv->ref_clk); in cs2000_clk_register()
506 parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); in cs2000_clk_register()
/linux/include/linux/platform_data/
H A Dnet-cw1200.h13 u16 ref_clk; /* REQUIRED (in KHz) */ member
26 u16 ref_clk; /* REQUIRED (in KHz) */ member
44 .ref_clk = 38400,
67 .ref_clk = 38400,
/linux/drivers/net/wireless/ath/ath10k/
H A Dahb.c96 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); in ath10k_ahb_clock_init()
97 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { in ath10k_ahb_clock_init()
99 PTR_ERR(ar_ahb->ref_clk)); in ath10k_ahb_clock_init()
100 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; in ath10k_ahb_clock_init()
118 ar_ahb->ref_clk = NULL; in ath10k_ahb_clock_deinit()
128 IS_ERR_OR_NULL(ar_ahb->ref_clk) || in ath10k_ahb_clock_enable()
141 ret = clk_prepare_enable(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
156 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_enable()
171 clk_disable_unprepare(ar_ahb->ref_clk); in ath10k_ahb_clock_disable()
[all...]
/linux/drivers/phy/
H A Dphy-snps-eusb2.c167 struct clk *ref_clk; member
249 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in exynos_eusb2_ref_clk_init()
286 unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk); in qcom_eusb2_ref_clk_init()
331 /* update ref_clk related registers */ in exynos_snps_eusb2_hsphy_init()
388 /* update ref_clk related registers */ in qcom_snps_eusb2_hsphy_init()
566 phy->ref_clk = NULL; in snps_eusb2_hsphy_probe()
569 phy->ref_clk = phy->clks[i].clk; in snps_eusb2_hsphy_probe()
574 if (IS_ERR_OR_NULL(phy->ref_clk)) { in snps_eusb2_hsphy_probe()
575 ret = phy->ref_clk ? PTR_ERR(phy->ref_clk) in snps_eusb2_hsphy_probe()
[all...]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c534 u32 mask, data, ref_clk; in mvebu_a3700_comphy_sata_power_on() local
561 ref_clk = REF_FREF_SEL_SERDES_40MHZ; in mvebu_a3700_comphy_sata_power_on()
563 ref_clk = REF_FREF_SEL_SERDES_25MHZ; in mvebu_a3700_comphy_sata_power_on()
565 data = ref_clk | COMPHY_MODE_SATA; in mvebu_a3700_comphy_sata_power_on()
823 u32 mask, data, cfg, ref_clk; in mvebu_a3700_comphy_usb3_power_on() local
901 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; in mvebu_a3700_comphy_usb3_power_on()
904 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; in mvebu_a3700_comphy_usb3_power_on()
909 PU_TX_INTP_BIT | PU_DFE_BIT | COMPHY_MODE_USB3 | ref_clk; in mvebu_a3700_comphy_usb3_power_on()
988 u32 mask, data, ref_clk; in mvebu_a3700_comphy_pcie_power_on() local
1034 ref_clk in mvebu_a3700_comphy_pcie_power_on()
[all...]
/linux/Documentation/devicetree/bindings/spi/
H A Djcore,spi.txt15 - clocks: If a phandle named "ref_clk" is present, SPI clock speed
33 clock-names = "ref_clk";
/linux/Documentation/devicetree/bindings/rtc/
H A Dcdns,rtc.txt12 - ref_clk: reference 1Hz or 100Hz clock, depending on IP configuration
20 clock-names = "pclk", "ref_clk";
/linux/drivers/spi/
H A Dspi-cadence.c104 * @ref_clk: Pointer to the peripheral clock
106 * @clk_rate: Reference clock frequency, taken from @ref_clk
119 struct clk *ref_clk; member
604 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk"); in cdns_spi_probe()
605 if (IS_ERR(xspi->ref_clk)) { in cdns_spi_probe()
606 dev_err(&pdev->dev, "ref_clk clock not found.\n"); in cdns_spi_probe()
607 ret = PTR_ERR(xspi->ref_clk); in cdns_spi_probe()
661 xspi->clk_rate = clk_get_rate(xspi->ref_clk); in cdns_spi_probe()
764 ret = clk_prepare_enable(xspi->ref_clk); in cdns_spi_runtime_resume()
[all...]
/linux/drivers/clk/baikal-t1/
H A Dccu-pll.c64 static inline unsigned long ccu_pll_lock_delay_us(unsigned long ref_clk, in ccu_pll_lock_delay_us() argument
69 do_div(us, ref_clk); in ccu_pll_lock_delay_us()
74 static inline unsigned long ccu_pll_calc_freq(unsigned long ref_clk, in ccu_pll_calc_freq() argument
79 u64 tmp = ref_clk; in ccu_pll_calc_freq()
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
94 ud = ccu_pll_lock_delay_us(ref_clk, nr); in ccu_pll_reset()
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c437 * @ref_clk: phy reference clock
457 struct clk *ref_clk; member
689 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
723 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
828 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
829 * ref_clk only. in qusb2_phy_init()
851 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
887 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
909 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
1012 qphy->ref_clk in qusb2_phy_probe()
[all...]
/linux/drivers/clk/tegra/
H A Dclk-dfll.c190 * REF_CLK_CYC_PER_DVCO_SAMPLE: the number of ref_clk cycles that the hardware
271 struct clk *ref_clk; member
394 ret = clk_enable(td->ref_clk); in tegra_dfll_runtime_resume()
403 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
411 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
430 clk_disable(td->ref_clk); in tegra_dfll_runtime_suspend()
1426 td->ref_clk = devm_clk_get(td->dev, "ref"); in dfll_init_clks()
1427 if (IS_ERR(td->ref_clk)) { in dfll_init_clks()
1429 return PTR_ERR(td->ref_clk); in dfll_init_clks()
1461 td->ref_rate = clk_get_rate(td->ref_clk); in dfll_init()
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