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Searched refs:rc_range_params (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c329 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, in dsc_write_to_registers()
330 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, in dsc_write_to_registers()
331 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
334 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, in dsc_write_to_registers()
335 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, in dsc_write_to_registers()
336 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
337 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, in dsc_write_to_registers()
338 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, in dsc_write_to_registers()
339 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); in dsc_write_to_registers()
342 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[ in dsc_write_to_registers()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c329 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); in dsc_log_pps()
330 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); in dsc_log_pps()
331 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); in dsc_log_pps()
707 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, in dsc_write_to_registers()
708 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, in dsc_write_to_registers()
709 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
712 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, in dsc_write_to_registers()
713 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, in dsc_write_to_registers()
714 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
715 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[ in dsc_write_to_registers()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Drc_calc_dpi.c54 memcpy(&to->rc_range_params, &from->rc_range_params, sizeof(from->rc_range_params)); in copy_pps_fields()
84 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; in copy_rc_to_cfg()
85 dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i]; in copy_rc_to_cfg()
87 dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; in copy_rc_to_cfg()
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c248 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << in drm_dsc_pps_payload_pack()
250 (dsc_cfg->rc_range_params[i].range_max_qp << in drm_dsc_pps_payload_pack()
252 (dsc_cfg->rc_range_params[i].range_bpg_offset)); in drm_dsc_pps_payload_pack()
340 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; member
1286 vdsc_cfg->rc_range_params[i].range_min_qp = in drm_dsc_setup_rc_params()
1287 rc_params->rc_range_params[i].range_min_qp; in drm_dsc_setup_rc_params()
1288 vdsc_cfg->rc_range_params[i].range_max_qp = in drm_dsc_setup_rc_params()
1289 rc_params->rc_range_params[i].range_max_qp; in drm_dsc_setup_rc_params()
1294 vdsc_cfg->rc_range_params[i].range_bpg_offset = in drm_dsc_setup_rc_params()
1295 rc_params->rc_range_params[ in drm_dsc_setup_rc_params()
[all...]
/linux/include/drm/display/
H A Ddrm_dsc.h175 * @rc_range_params:
179 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; member
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.c131 struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params; in dpu_hw_dsc_config_thresh()
H A Ddpu_hw_dsc_1_2.c255 rc = dsc->rc_range_params; in dpu_hw_dsc_config_thresh_1_2()