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Searched refs:nvif_rd32 (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/nouveau/nvif/
H A Duserc361.c30 hi = nvif_rd32(&user->object, 0x084); in nvif_userc361_time()
31 lo = nvif_rd32(&user->object, 0x080); in nvif_userc361_time()
32 } while (hi != nvif_rd32(&user->object, 0x084)); in nvif_userc361_time()
H A Dchan506f.c37 return nvif_rd32(&chan->userd, 0x88); in nvif_chan506f_gpfifo_read_get()
43 u32 tlgetlo = nvif_rd32(&chan->userd, 0x58); in nvif_chan506f_read_get()
44 u32 tlgethi = nvif_rd32(&chan->userd, 0x5c); in nvif_chan506f_read_get()
H A Dchan906f.c56 return nvif_rd32(&chan->sema, 0) >> NVIF_CHAN906F_GPPTR_SHIFT; in nvif_chan906f_gpfifo_read_get()
62 return nvif_rd32(&chan->sema, 0) & NVIF_CHAN906F_PBPTR_MASK; in nvif_chan906f_read_get()
H A Dchanc36f.c19 nvif_rd32(&chan->userd, 0); /* ensure BAR1 writes are flushed to vidmem */ in nvif_chanc36f_gpfifo_kick()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_svm.c457 const u32 instlo = nvif_rd32(memory, offset + 0x00); in nouveau_svm_fault_cache()
458 const u32 insthi = nvif_rd32(memory, offset + 0x04); in nouveau_svm_fault_cache()
459 const u32 addrlo = nvif_rd32(memory, offset + 0x08); in nouveau_svm_fault_cache()
460 const u32 addrhi = nvif_rd32(memory, offset + 0x0c); in nouveau_svm_fault_cache()
461 const u32 timelo = nvif_rd32(memory, offset + 0x10); in nouveau_svm_fault_cache()
462 const u32 timehi = nvif_rd32(memory, offset + 0x14); in nouveau_svm_fault_cache()
463 const u32 engine = nvif_rd32(memory, offset + 0x18); in nouveau_svm_fault_cache()
464 const u32 info = nvif_rd32(memory, offset + 0x1c); in nouveau_svm_fault_cache()
734 buffer->put = nvif_rd32(device, buffer->putaddr); in nouveau_svm_fault()
735 buffer->get = nvif_rd32(devic in nouveau_svm_fault()
[all...]
H A Dnouveau_led.c44 div = nvif_rd32(device, 0x61c880) & 0x00ffffff; in nouveau_led_get_brightness()
45 duty = nvif_rd32(device, 0x61c884) & 0x00ffffff; in nouveau_led_get_brightness()
H A Dnouveau_backlight.c69 int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & in nv40_get_intensity()
82 int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); in nv40_set_intensity()
104 if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) in nv40_backlight_init()
H A Dnouveau_dma.c45 val = nvif_rd32(chan->userd, chan->user_get); in READ_GET()
H A Dnouveau_bios.c240 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in call_lvds_script()
336 return nvif_rd32(device, 0x001800) & 0x0000000f; in get_fp_strap()
339 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; in get_fp_strap()
341 return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; in get_fp_strap()
671 sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; in run_tmds_table()
1955 nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); in load_nv17_hwsq_ucode_entry()
H A Dnouveau_debugfs.c63 nvif_rd32(&drm->client.device.object, 0x101000)); in nouveau_debugfs_strap_peek()
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c202 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); in nv04_update_arb()
223 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; in nv04_update_arb()
224 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; in nv04_update_arb()
H A Dhw.h66 val = nvif_rd32(device, reg); in NVReadCRTC()
86 val = nvif_rd32(device, reg); in NVReadRAMDAC()
265 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28)); in nv_heads_tied()
H A Dhw.c178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
180 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
184 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
750 if ( (nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) in nv_load_state_ext()
754 if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) in nv_load_state_ext()
H A Dtvnv17.h140 return nvif_rd32(&device->object, reg); in nv_read_ptv()
H A Doverlay.c434 nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); in nv04_update_plane()
H A Ddfp.c340 if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) in nv04_dfp_mode_set()
/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dobject.h56 #define nvif_rd32(a,b) ({ ((u32)nvif_rd((a), ioread32_native, 4, (b))); }) macro
62 u32 _addr = (b), _data = nvif_rd32(__object, _addr); \
114 #define NVIF_RD32_(p,o,dr) nvif_rd32((p), (o) + (dr))
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dsorc37d.c45 u32 tmp = nvif_rd32(&disp->caps, 0x000144 + (or * 8)); in sorc37d_get_caps()
H A Ddisp.c147 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) in nv50_dmac_kick()