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Searched refs:cw4 (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c125 const struct dmub_window *cw4, in dmub_dcn30_setup_windows() argument
159 offset = cw4->offset; in dmub_dcn30_setup_windows()
165 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn30_setup_windows()
167 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn30_setup_windows()
174 cw4->region.top - cw4->region.base - 1, in dmub_dcn30_setup_windows()
H A Ddmub_dcn20.c192 const struct dmub_window *cw4, in dmub_dcn20_setup_windows() argument
229 dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
235 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn20_setup_windows()
237 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn20_setup_windows()
244 cw4->region.top - cw4->region.base - 1, in dmub_dcn20_setup_windows()
H A Ddmub_dcn30.h44 const struct dmub_window *cw4,
H A Ddmub_dcn31.c193 const struct dmub_window *cw4, in dmub_dcn31_setup_windows() argument
209 offset = cw4->offset; in dmub_dcn31_setup_windows()
213 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn31_setup_windows()
215 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn31_setup_windows()
H A Ddmub_dcn35.c220 const struct dmub_window *cw4, in dmub_dcn35_setup_windows() argument
236 offset = cw4->offset; in dmub_dcn35_setup_windows()
240 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn35_setup_windows()
242 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn35_setup_windows()
H A Ddmub_dcn32.c217 const struct dmub_window *cw4, in dmub_dcn32_setup_windows() argument
233 offset = cw4->offset; in dmub_dcn32_setup_windows()
237 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn32_setup_windows()
239 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn32_setup_windows()
H A Ddmub_srv.c660 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; in dmub_srv_hw_init() local
716 cw4.offset.quad_part = mail_fb->gpu_addr; in dmub_srv_hw_init()
717 cw4.region.base = DMUB_CW4_BASE; in dmub_srv_hw_init()
718 cw4.region.top = cw4.region.base + mail_fb->size; in dmub_srv_hw_init()
727 inbox1.base = cw4.region.base; in dmub_srv_hw_init()
728 inbox1.top = cw4.region.base + DMUB_RB_SIZE; in dmub_srv_hw_init()
756 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, &region6); in dmub_srv_hw_init()
H A Ddmub_dcn401.c200 const struct dmub_window *cw4, in dmub_dcn401_setup_windows() argument
216 offset = cw4->offset; in dmub_dcn401_setup_windows()
220 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); in dmub_dcn401_setup_windows()
222 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, in dmub_dcn401_setup_windows()
H A Ddmub_dcn20.h198 const struct dmub_window *cw4,
H A Ddmub_dcn31.h200 const struct dmub_window *cw4,
H A Ddmub_dcn32.h207 const struct dmub_window *cw4,
H A Ddmub_dcn35.h220 const struct dmub_window *cw4,
H A Ddmub_dcn401.h217 const struct dmub_window *cw4,