Searched refs:Post (Results 1 – 25 of 40) sorted by relevance
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19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |33 Video Post Processing37 :doc: Video Post Processing
51 Post image processor (improc)53 Post image processor adjusts frame data like gamma and color space to fit the
21 memory media. Post Package Repair (PPR) and memory sparing are examples of24 Post Package Repair (PPR)27 Post Package Repair is a maintenance operation which requests the memory141 2. CXL memory Soft Post Package Repair (sPPR)143 Post Package Repair (PPR) maintenance operations may be supported by CXL
27 4. Post Package Repair (PPR) control
28 movq %rsp,8(%rdi) # Post-return %rsp!
31 movl %esp,4(%edx) # Post-return %esp!
29 Post on netdev if something is unclear.
8 PPR (Post Package Repair), memory sparing etc, where <dev-name>12 Post Package Repair is a maintenance operation requests the memory43 - ppr - Post package repair.
42 * Post-patch51 * Post-unpatch
65 # Post Resume Delay
66 # Post Resume Delay
93 # Post Resume Delay
125 - Post the packet to IOP by writing it to inbound queue. For requests171 - Post the inbound list writer pointer to IOP.
26 [2-2-2] Post transportt->eh_strategy_handler() SCSI midlayer conditions449 2.2.2 Post transportt->eh_strategy_handler() SCSI midlayer conditions
130 Note that some Intel CPUs are susceptible to Post-barrier Return238 .. [#intel-ibpb-rsb] "Introduction" in `Post-barrier Return Stack Buffer Predictions / CVE-2022-26373 / INTEL-SA-00706 <https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/post-barrier-return-stack-buffer-predictions.html>`_248 .. [#intel-pbrsb] `Post-barrier Return Stack Buffer Predictions / CVE-2022-26373 / INTEL-SA-00706 <https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/post-barrier-return-stack-buffer-predictions.html>`_
4869 uint32_t Post; in ips_init_morpheus() local 4877 /* Wait up to 45 secs for Post */ in ips_init_morpheus() 4896 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus() 4898 if (Post == 0x4F00) { /* If Flashing the Battery PIC */ in ips_init_morpheus() 4907 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus() 4908 if (Post != 0x4F00) in ips_init_morpheus() 4926 if (Post < (IPS_GOOD_POST_STATUS << 8)) { in ips_init_morpheus() 4928 "reset controller fails (post status %x).\n", Post); in ips_init_morpheus() 4966 if (Post == 0xEF10) { in ips_init_morpheus()
121 Post