| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.c | 201 bool Interlace,
502 bool Interlace[],
673 bool Interlace,
1754 bool Interlace, argument
1767 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
2374 v->Interlace[k],
2431 v->Interlace[k],
2568 v->Interlace[k],
2627 myPipe.InterlaceEnable = v->Interlace[k];
3169 isInterlaceTiming = (v->Interlace[
6409 CalculateStutterEfficiency(struct display_mode_lib * mode_lib,int CompressedBufferSizeInkByte,bool UnboundedRequestEnabled,int ConfigReturnBufferSizeInKByte,int MetaFIFOSizeInKEntries,int ZeroSizeBufferEntries,int NumberOfActivePlanes,int ROBBufferSizeInKByte,double TotalDataReadBandwidth,double DCFCLK,double ReturnBW,double COMPBUF_RESERVED_SPACE_64B,double COMPBUF_RESERVED_SPACE_ZS,double SRExitTime,double SRExitZ8Time,bool SynchronizedVBlank,double Z8StutterEnterPlusExitWatermark,double StutterEnterPlusExitWatermark,bool ProgressiveToInterlaceUnitInOPP,bool Interlace[],double MinTTUVBlank[],int DPPPerPlane[],unsigned int DETBufferSizeY[],int BytePerPixelY[],double BytePerPixelDETY[],double SwathWidthY[],int SwathHeightY[],int SwathHeightC[],double NetDCCRateLuma[],double NetDCCRateChroma[],double DCCFractionOfZeroSizeRequestsLuma[],double DCCFractionOfZeroSizeRequestsChroma[],int HTotal[],int VTotal[],double PixelClock[],double VRatio[],enum scan_direction_class SourceScan[],int BlockHeight256BytesY[],int BlockWidth256BytesY[],int BlockHeight256BytesC[],int BlockWidth256BytesC[],int DCCYMaxUncompressedBlock[],int DCCCMaxUncompressedBlock[],int VActive[],bool DCCEnable[],bool WritebackEnable[],double ReadBandwidthPlaneLuma[],double ReadBandwidthPlaneChroma[],double meta_row_bw[],double dpte_row_bw[],double * StutterEfficiencyNotIncludingVBlank,double * StutterEfficiency,int * NumberOfStutterBurstsPerFrame,double * Z8StutterEfficiencyNotIncludingVBlank,double * Z8StutterEfficiency,int * Z8NumberOfStutterBurstsPerFrame,double * StutterPeriod) global() argument
7323 CalculateMaxVStartup(unsigned int VTotal,unsigned int VActive,unsigned int VBlankNom,unsigned int HTotal,double PixelClock,bool ProgressiveTointerlaceUnitinOPP,bool Interlace,unsigned int VBlankNomDefaultUS,double WritebackDelayTime) global() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_mode_vba_20v2.c | 85 bool Interlace,
150 bool Interlace,
492 bool Interlace, in CalculateDelayAfterScaler()
529 if (OutputFormat == dm_420 || (Interlace && ProgressiveToInterlaceUnitInOPP)) in CalculateDelayAfterScaler()
873 bool Interlace, in CalculatePrefetchSourceLines() argument
885 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
1930 mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1972 mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2129 mode_lib->vba.SwathWidthSingleDPPY[k], mode_lib->vba.BytePerPixelDETY[k], mode_lib->vba.BytePerPixelDETC[k], mode_lib->vba.SwathHeightY[k], mode_lib->vba.SwathHeightC[k], mode_lib->vba.Interlace[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2174 mode_lib->vba.Interlace[ in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
463 CalculateDelayAfterScaler(struct display_mode_lib * mode_lib,double ReturnBW,double ReadBandwidthPlaneLuma,double ReadBandwidthPlaneChroma,double TotalDataReadBandwidth,double DisplayPipeLineDeliveryTimeLuma,double DisplayPipeLineDeliveryTimeChroma,double DPPCLK,double DISPCLK,double PixelClock,unsigned int DSCDelay,unsigned int DPPPerPlane,bool ScalerEnabled,unsigned int NumberOfCursors,double DPPCLKDelaySubtotal,double DPPCLKDelaySCL,double DPPCLKDelaySCLLBOnly,double DPPCLKDelayCNVCFormater,double DPPCLKDelayCNVCCursor,double DISPCLKDelaySubtotal,unsigned int ScalerRecoutWidth,enum output_format_class OutputFormat,unsigned int HTotal,unsigned int SwathWidthSingleDPPY,double BytePerPixelDETY,double BytePerPixelDETC,unsigned int SwathHeightY,unsigned int SwathHeightC,bool Interlace,bool ProgressiveToInterlaceUnitInOPP,double * DSTXAfterScaler,double * DSTYAfterScaler) CalculateDelayAfterScaler() argument
[all...] |
| H A D | display_mode_vba_20.c | 126 bool Interlace,
813 bool Interlace, in CalculatePrefetchSourceLines() argument
825 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
1894 mode_lib->vba.Interlace[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1936 mode_lib->vba.Interlace[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2140 mode_lib->vba.Interlace[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4172 && mode_lib->vba.Interlace[k] == true in dml20_ModeSupportAndSystemConfigurationFull()
4527 mode_lib->vba.Interlace[k], in dml20_ModeSupportAndSystemConfigurationFull()
4566 mode_lib->vba.Interlace[k], in dml20_ModeSupportAndSystemConfigurationFull()
4757 mode_lib->vba.Interlace[ in dml20_ModeSupportAndSystemConfigurationFull()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 192 bool Interlace,
493 bool Interlace[],
1737 bool Interlace, argument
1750 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
2355 v->Interlace[k],
2412 v->Interlace[k],
2542 (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
2608 myPipe.InterlaceEnable = v->Interlace[k];
3150 isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
3225 v->Interlace,
6314 CalculateStutterEfficiency(struct display_mode_lib * mode_lib,int CompressedBufferSizeInkByte,bool UnboundedRequestEnabled,int ConfigReturnBufferSizeInKByte,int MetaFIFOSizeInKEntries,int ZeroSizeBufferEntries,int NumberOfActivePlanes,int ROBBufferSizeInKByte,double TotalDataReadBandwidth,double DCFCLK,double ReturnBW,double COMPBUF_RESERVED_SPACE_64B,double COMPBUF_RESERVED_SPACE_ZS,double SRExitTime,double SRExitZ8Time,bool SynchronizedVBlank,double Z8StutterEnterPlusExitWatermark,double StutterEnterPlusExitWatermark,bool ProgressiveToInterlaceUnitInOPP,bool Interlace[],double MinTTUVBlank[],int DPPPerPlane[],unsigned int DETBufferSizeY[],int BytePerPixelY[],double BytePerPixelDETY[],double SwathWidthY[],int SwathHeightY[],int SwathHeightC[],double NetDCCRateLuma[],double NetDCCRateChroma[],double DCCFractionOfZeroSizeRequestsLuma[],double DCCFractionOfZeroSizeRequestsChroma[],int HTotal[],int VTotal[],double PixelClock[],double VRatio[],enum scan_direction_class SourceScan[],int BlockHeight256BytesY[],int BlockWidth256BytesY[],int BlockHeight256BytesC[],int BlockWidth256BytesC[],int DCCYMaxUncompressedBlock[],int DCCCMaxUncompressedBlock[],int VActive[],bool DCCEnable[],bool WritebackEnable[],double ReadBandwidthPlaneLuma[],double ReadBandwidthPlaneChroma[],double meta_row_bw[],double dpte_row_bw[],double * StutterEfficiencyNotIncludingVBlank,double * StutterEfficiency,int * NumberOfStutterBurstsPerFrame,double * Z8StutterEfficiencyNotIncludingVBlank,double * Z8StutterEfficiency,int * Z8NumberOfStutterBurstsPerFrame,double * StutterPeriod) global() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_utils.c | 45 dml_timing_array->Interlace[dst_index] = dml_timing_array->Interlace[src_index]; in dml2_util_copy_dml_timing()
|
| H A D | display_mode_core_structs.h | 613 dml_bool_t Interlace[__DML_NUM_PLANES__]; member
1301 dml_bool_t *Interlace; member
1544 dml_bool_t *Interlace; member
|
| H A D | dml_display_rq_dlg_calc.c | 215 dml_bool_t interlaced = timing->Interlace[plane_idx]; in dml_rq_dlg_get_dlg_reg()
|
| H A D | display_mode_util.c | 538 dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing->Interlace[i]); in dml_print_dml_display_cfg_timing()
|
| H A D | dml2_translation_helper.c | 765 out->Interlace[location] = in->timing.flags.INTERLACE; in populate_dml_timing_cfg_from_stream_state()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_32.c | 437 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.SurfaceParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
696 v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] && in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
774 v->dummy_vars.DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation.myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1439 isInterlaceTiming = (mode_lib->vba.Interlace[k] && in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1533 mode_lib->vba.Interlace, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1597 mode_lib->vba.Interlace, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2357 == dm_420 && mode_lib->vba.Interlace[k] == 1 && in dml32_ModeSupportAndSystemConfigurationFull()
2730 v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.SurfParameters[k].InterlaceEnable = mode_lib->vba.Interlace[k]; in dml32_ModeSupportAndSystemConfigurationFull()
2962 mode_lib->vba.MaximumVStartup[i][j][k] = ((mode_lib->vba.Interlace[k] && in dml32_ModeSupportAndSystemConfigurationFull()
3083 mode_lib->vba.Interlace, in dml32_ModeSupportAndSystemConfigurationFull()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.c | 175 bool Interlace,
1612 bool Interlace, in CalculatePrefetchSourceLines() argument
1624 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
2224 v->Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2281 v->Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2431 myPipe.InterlaceEnable = v->Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4175 || (v->OutputFormat[k] == dm_420 && v->Interlace[k] == true && v->ProgressiveToInterlaceUnitInOPP == true))) { in dml30_ModeSupportAndSystemConfigurationFull()
4402 v->Interlace[k], in dml30_ModeSupportAndSystemConfigurationFull()
4457 v->Interlace[k], in dml30_ModeSupportAndSystemConfigurationFull()
4764 myPipe.InterlaceEnable = v->Interlace[ in dml30_ModeSupportAndSystemConfigurationFull()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_mode_vba_21.c | 164 bool Interlace,
1212 bool Interlace, in CalculatePrefetchSourceLines() argument
1224 *VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1); in CalculatePrefetchSourceLines()
1865 mode_lib->vba.Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1921 mode_lib->vba.Interlace[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2148 myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3442 myPipe.InterlaceEnable = mode_lib->vba.Interlace[k]; in CalculatePrefetchSchedulePerPlane()
4387 && mode_lib->vba.Interlace[k] == true in dml21_ModeSupportAndSystemConfigurationFull()
4637 mode_lib->vba.Interlace[k], in dml21_ModeSupportAndSystemConfigurationFull()
4693 mode_lib->vba.Interlace[ in dml21_ModeSupportAndSystemConfigurationFull()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 594 mode_lib->vba.Interlace[mode_lib->vba.NumberOfActivePlanes] = dst->interlaced; in fetch_pipe_params()
1052 //Progressive To Interlace Unit Effect in PixelClockAdjustmentForProgressiveToInterlaceUnit()
1055 if (mode_lib->vba.Interlace[k] == 1 in PixelClockAdjustmentForProgressiveToInterlaceUnit()
|
| H A D | display_mode_vba.h | 498 bool Interlace[DC__NUM_DPP__MAX]; member
|
| /linux/drivers/gpu/drm/amd/display/dc/bios/ |
| H A D | bios_parser.c | 1293 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; in get_embedded_panel_info_v1_2()
1411 lvds->sLCDTiming.susModeMiscInfo.sbfAccess.Interlace; in get_embedded_panel_info_v1_3()
|
| /linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 3246 USHORT Interlace:1; member
3262 USHORT Interlace:1;
|
| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 3723 USHORT Interlace:1; member
3739 USHORT Interlace:1;
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 432 //Progressive To Interlace Unit Effect in PixelClockAdjustmentForProgressiveToInterlaceUnit()
1818 bool Interlace, in CalculatePrefetchSourceLines() argument
1850 *VInitPreFill = (unsigned int)(math_floor2((VRatio + (double)VTaps + 1 + (Interlace ? 1 : 0) * 0.5 * VRatio) / 2.0, 1)); in CalculatePrefetchSourceLines()
|