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Searched refs:GEN3_RELATED_OFF (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/pci/controller/dwc/
H A Dpcie-qcom-common.c16 * GEN3_RELATED_OFF register is repurposed to apply equalization in qcom_pcie_common_set_16gt_equalization()
18 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF in qcom_pcie_common_set_16gt_equalization()
22 reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in qcom_pcie_common_set_16gt_equalization()
27 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); in qcom_pcie_common_set_16gt_equalization()
H A Dpcie-tegra194.c863 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in config_gen3_gen4_eq_presets()
865 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); in config_gen3_gen4_eq_presets()
873 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in config_gen3_gen4_eq_presets()
876 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); in config_gen3_gen4_eq_presets()
885 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in config_gen3_gen4_eq_presets()
887 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); in config_gen3_gen4_eq_presets()
941 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in tegra_pcie_dw_host_init()
943 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); in tegra_pcie_dw_host_init()
1867 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in pex_ep_event_pex_rst_deassert()
1869 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, va in pex_ep_event_pex_rst_deassert()
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H A Dpcie-designware.h120 #define GEN3_RELATED_OFF 0x890 macro
H A Dpci-imx6.c1311 * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] in imx_pcie_host_post_init()
1316 * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] in imx_pcie_host_post_init()
1320 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); in imx_pcie_host_post_init()
1322 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); in imx_pcie_host_post_init()
H A Dpcie-qcom.c1220 pci->dbi_base + GEN3_RELATED_OFF); in qcom_pcie_post_init_2_9_0()