Searched refs:FPU_CSR_ALL_E (Results 1 – 8 of 8) sorted by relevance
183 ((fcr31 & FPU_CSR_ALL_E) << in mask_fcr31_x() 184 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)))); in mask_fcr31_x()
1327 #define FPU_CSR_ALL_E 0x00000f80 macro
65 return fcsr & ((fcsr & FPU_CSR_ALL_E) << in mask_fcsr_x() 66 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E))); in mask_fcsr_x()
1516 #define FPU_CSR_ALL_E 0x0000001f macro
866 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM); in cop1_cfc() 932 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM); in cop1_ctc() 935 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM); in cop1_ctc() 1179 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { in cop1Emulate() 1567 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { in fpux_emu() 2765 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) { in fpu_emu()
35 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; in cpu_set_fpu_fcsr_mask()
355 enabled = ((csr & FPU_CSR_ALL_E) << 24); in fcsr_pending()
503 enabled = FPU_CSR_UNI_X | ((csr & FPU_CSR_ALL_E) << 5); in fpcsr_pending()