| /linux/drivers/net/ethernet/cavium/thunder/ |
| H A D | thunder_xcv.c | 72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
94 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
102 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
106 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
130 writeq_relaxed(cfg, xcv->reg_base + XCV_CTL); in xcv_setup_link()
135 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_setup_link()
140 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_setup_link()
143 writeq_relaxed( in xcv_setup_link()
[all...] |
| H A D | nic_main.c | 81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
90 writeq_relaxed(val, nic->reg_base + offset); in nic_reg_write()
146 writeq_relaxed(msg[0], mbx_addr); in nic_send_msg_to_vf()
147 writeq_relaxed(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
149 writeq_relaxed(msg[1], mbx_addr + 8); in nic_send_msg_to_vf()
150 writeq_relaxed(msg[0], mbx_addr); in nic_send_msg_to_vf()
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| /linux/drivers/perf/ |
| H A D | marvell_cn10k_ddr_pmu.c | 509 writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base + in cn10k_ddr_perf_counter_start()
519 writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base + in cn10k_ddr_perf_counter_stop()
547 writeq_relaxed(val, pmu->base + reg); in cn10k_ddr_perf_counter_enable()
556 writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, in cn10k_ddr_perf_counter_enable()
649 writeq_relaxed(val, pmu->base + reg_offset); in cn10k_ddr_perf_event_add()
702 writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base + in cn10k_ddr_perf_pmu_enable()
711 writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base + in cn10k_ddr_perf_pmu_disable()
748 writeq_relaxed(val, pmu->base + p_data->cnt_freerun_en); in ddr_pmu_enable_read_freerun()
762 writeq_relaxed(val, pmu->base + p_data->cnt_freerun_en); in ddr_pmu_enable_write_freerun()
771 writeq_relaxed(va in ddr_pmu_read_clear_freerun()
[all...] |
| H A D | marvell_cn10k_tad_pmu.c | 80 writeq_relaxed(0, tad_pmu->regions[i].base + in tad_pmu_event_counter_stop()
101 writeq_relaxed(0, tad_pmu->regions[i].base + in tad_pmu_event_counter_start()
109 writeq_relaxed(reg_val, tad_pmu->regions[i].base + in tad_pmu_event_counter_start()
|
| H A D | arm_smmuv3_pmu.c | 734 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); in smmu_pmu_write_msi_msg()
746 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0); in smmu_pmu_setup_msi()
785 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
787 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
789 writeq_relaxed(counter_present_mask, in smmu_pmu_reset()
|
| H A D | arm-cmn.c | 1468 writeq_relaxed(CMN_CC_INIT, pmccntr); in arm_cmn_read_cc()
1555 writeq_relaxed(le64_to_cpu(dn->event_sel_w), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_set_event_sel_lo()
1575 writeq_relaxed(CMN_CC_INIT, CMN_DT_PMCCNTR(dtc)); in arm_cmn_event_start()
1585 writeq_relaxed(val, base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_start()
1586 writeq_relaxed(mask, base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_start()
1614 writeq_relaxed(0, base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_stop()
1615 writeq_relaxed(~0ULL, base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_stop()
1954 writeq_relaxed(reg, dtm->base + CMN_DTM_PMU_CONFIG); in arm_cmn_event_add()
2120 writeq_relaxed(dtm->pmu_config_low, dtm->base + CMN_DTM_PMU_CONFIG); in arm_cmn_init_dtm()
2123 writeq_relaxed( in arm_cmn_init_dtm()
[all...] |
| /linux/drivers/iommu/arm/arm-smmu/ |
| H A D | arm-smmu-qcom-debug.c | 213 writeq_relaxed(val, tbu->base + DEBUG_SID_HALT_REG); in qcom_tbu_trigger_atos()
214 writeq_relaxed(iova, tbu->base + DEBUG_VA_ADDR_REG); in qcom_tbu_trigger_atos()
216 writeq_relaxed(val, tbu->base + DEBUG_AXUSER_REG); in qcom_tbu_trigger_atos()
228 writeq_relaxed(val, tbu->base + DEBUG_TXN_TRIGG_REG); in qcom_tbu_trigger_atos()
254 writeq_relaxed(0, tbu->base + DEBUG_TXN_TRIGG_REG); in qcom_tbu_trigger_atos()
255 writeq_relaxed(0, tbu->base + DEBUG_VA_ADDR_REG); in qcom_tbu_trigger_atos()
|
| /linux/include/linux/ |
| H A D | io-64-nonatomic-lo-hi.h | 54 #ifndef writeq_relaxed
55 #define writeq_relaxed lo_hi_writeq_relaxed macro
|
| H A D | io-64-nonatomic-hi-lo.h | 54 #ifndef writeq_relaxed
55 #define writeq_relaxed hi_lo_writeq_relaxed macro
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| /linux/arch/arm64/kernel/ |
| H A D | smp_spin_table.c | 92 writeq_relaxed(pa_holding_pen, release_addr); in smp_spin_table_cpu_prepare()
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| H A D | acpi_parking_protocol.c | 102 writeq_relaxed(__pa_symbol(secondary_entry), in acpi_parking_protocol_cpu_boot()
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| /linux/tools/testing/selftests/kvm/include/arm64/ |
| H A D | processor.h | 238 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) macro
243 #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c));})
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| /linux/drivers/iommu/riscv/ |
| H A D | iommu.h | 79 writeq_relaxed((val), (iommu)->reg + (addr))
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| /linux/tools/testing/selftests/kvm/lib/arm64/ |
| H A D | gic_v3.c | 417 writeq_relaxed(val, rdist_base + GICR_PROPBASER); in gic_rdist_enable_lpis()
422 writeq_relaxed(val, rdist_base + GICR_PENDBASER); in gic_rdist_enable_lpis()
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| H A D | gic_v3_its.c | 25 writeq_relaxed(val, GITS_BASE_GVA + offset); in its_write_u64()
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| /linux/drivers/soc/apple/ |
| H A D | mailbox.c | 153 writeq_relaxed(msg.msg0, mbox->regs + mbox->hw->a2i_send0); in apple_mbox_send()
154 writeq_relaxed(FIELD_PREP(APPLE_MBOX_MSG1_MSG, msg.msg1), in apple_mbox_send()
|
| /linux/rust/helpers/ |
| H A D | io.c | 105 writeq_relaxed(value, addr); in rust_helper_writeq_relaxed()
|
| /linux/arch/sh/include/asm/ |
| H A D | io.h | 46 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c)) macro
56 #define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
|
| /linux/include/asm-generic/ |
| H A D | io.h | 385 #if defined(writeq) && !defined(writeq_relaxed)
386 #define writeq_relaxed writeq_relaxed macro
387 static inline void writeq_relaxed(u64 value, volatile void __iomem *addr) in writeq_relaxed() function
|
| /linux/rust/kernel/ |
| H A D | io.rs | 263 writeq_relaxed <- u64
|
| /linux/drivers/bus/fsl-mc/ |
| H A D | mc-sys.c | 109 writeq_relaxed(le64_to_cpu(cmd->params[i]), &portal->params[i]); in mc_write_command()
|
| /linux/drivers/clocksource/ |
| H A D | timer-clint.c | 118 writeq_relaxed(clint_get_cycles64() + delta, r); in clint_clock_next_event()
|
| /linux/arch/riscv/include/asm/ |
| H A D | mmio.h | 125 #define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) macro
|
| /linux/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | tegra241-cmdqv.c | 459 writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, BASE)); in tegra241_vcmdq_hw_deinit()
460 writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, CONS_INDX_BASE)); in tegra241_vcmdq_hw_deinit()
483 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE)); in tegra241_vcmdq_hw_init()
1080 writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE)); in tegra241_vcmdq_hw_init_user()
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| /linux/drivers/hwtracing/intel_th/ |
| H A D | sth.c | 45 writeq_relaxed(*(u64 *)payload, dest); in sth_iowrite()
|