| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cdclk.c | 622 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
625 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
673 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
762 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
855 cdclk_config->voltage_level = in bdw_get_cdclk()
921 cdclk_config->voltage_level); in bdw_set_cdclk()
1062 cdclk_config->voltage_level = in skl_get_cdclk()
1224 cdclk_config->voltage_level); in skl_set_cdclk()
1295 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1306 cdclk_config.voltage_level in skl_cdclk_uninit_hw()
1591 int voltage_level; calc_voltage_level() local
2504 intel_pcode_notify(struct intel_display * display,u8 voltage_level,u8 active_pipe_count,u16 cdclk,bool cdclk_update_valid,bool pipe_count_update_valid) intel_pcode_notify() argument
2602 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; intel_cdclk_pcode_pre_notify() local
2647 unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; intel_cdclk_pcode_post_notify() local
[all...] |
| H A D | intel_cdclk.h | 20 u8 voltage_level; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 499 input->clks_cfg.voltage = v->voltage_level; in dcn_bw_calc_rq_dlg_ttu()
560 if (v->voltage_level < 2) {
590 if (v->voltage_level < 3) {
614 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
618 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
629 if (v->voltage_level >= 2) {
633 if (v->voltage_level >= 3)
1062 if (v->voltage_level != 0 in dcn_validate_bandwidth()
1069 if (v->voltage_level == 0 && in dcn_validate_bandwidth()
1122 if (v->voltage_level ! in dcn_validate_bandwidth()
[all...] |
| H A D | dcn_calc_auto.c | 1000 v->voltage_level = v->voltage_level_without_immediate_flip; in mode_support_and_system_configuration()
1004 v->voltage_level = v->voltage_level_with_immediate_flip; in mode_support_and_system_configuration()
1006 v->dcfclk = v->dcfclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1007 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level]; in mode_support_and_system_configuration()
1009 v->required_dispclk_per_ratio[j] = v->required_dispclk[v->voltage_level][j]; in mode_support_and_system_configuration()
1011 v->dpp_per_plane_per_ratio[j][k] = v->no_of_dpp[v->voltage_level][j][k]; in mode_support_and_system_configuration()
1013 v->dispclk_dppclk_support_per_ratio[j] = v->dispclk_dppclk_support[v->voltage_level][j]; in mode_support_and_system_configuration()
1015 v->max_phyclk = v->phyclk_per_state[v->voltage_level]; in mode_support_and_system_configuration()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top_types.h | 675 unsigned int voltage_level; // LEGACY_ONLY member
|
| /linux/drivers/gpu/drm/i915/ |
| H A D | i915_reg.h | 1126 #define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \ argument
1129 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | dcn_calcs.h | 211 int voltage_level; member
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4.c | 637 in_out->programming->informative.voltage_level = in_out->instance->scratch.mode_programming_locals.mode_programming_ex_params.min_clk_index; in core_dcn4_populate_informative()
639 in_out->programming->informative.voltage_level = in_out->instance->scratch.mode_support_locals.mode_support_ex_params.min_clk_index; in core_dcn4_populate_informative()
|
| /linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_atombios.c | 3105 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) in radeon_atom_set_voltage() argument
3109 u8 frev, crev, volt_index = voltage_level; in radeon_atom_set_voltage()
3115 if (voltage_level == 0xff01) in radeon_atom_set_voltage()
3127 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); in radeon_atom_set_voltage()
3132 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); in radeon_atom_set_voltage()
3340 u16 voltage_level, u8 voltage_type, in radeon_atom_get_voltage_gpio_settings() argument
3356 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); in radeon_atom_get_voltage_gpio_settings()
3364 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); in radeon_atom_get_voltage_gpio_settings()
|
| H A D | radeon.h | 302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
304 u16 voltage_level, u8 voltage_type,
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 1430 SMU71_Discrete_VoltageLevel voltage_level; in iceland_populate_smc_acpi_level() local
1504 if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level)) in iceland_populate_smc_acpi_level()
1506 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); in iceland_populate_smc_acpi_level()
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| H A D | ci_smumgr.c | 1384 SMU7_Discrete_VoltageLevel voltage_level; in ci_populate_smc_acpi_level() local
1458 if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level)) in ci_populate_smc_acpi_level()
1460 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
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| H A D | tonga_smumgr.c | 1182 SMIO_Pattern voltage_level; in tonga_populate_smc_acpi_level() local
1246 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level)) in tonga_populate_smc_acpi_level()
1248 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); in tonga_populate_smc_acpi_level()
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