Searched refs:vlv_cck_read (Results 1 – 4 of 4) sorted by relevance
/linux/drivers/gpu/drm/i915/display/ |
H A D | vlv_dsi_pll.c | 236 if (wait_for(vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & in vlv_dsi_pll_enable() 257 tmp = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); in vlv_dsi_pll_disable() 331 pll_ctl = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL); in vlv_dsi_get_pclk() 332 pll_div = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_DIVIDER); in vlv_dsi_get_pclk() 597 cur_state = vlv_cck_read(display->drm, CCK_REG_DSI_PLL_CONTROL) & DSI_PLL_VCO_EN; in assert_dsi_pll()
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H A D | vlv_sideband.h | 41 static inline u32 vlv_cck_read(struct drm_device *drm, u32 reg) in vlv_cck_read() function
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H A D | intel_cdclk.c | 719 val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk() 724 if (wait_for((vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
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H A D | intel_display.c | 149 hpll_freq = vlv_cck_read(drm, CCK_FUSE_REG) & in vlv_get_hpll_vco() 161 val = vlv_cck_read(drm, reg); in vlv_get_cck_clock()
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