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Searched refs:num_engines (Results 1 – 25 of 43) sorted by relevance

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/linux/drivers/gpu/drm/xe/
H A Dxe_gt_ccs_mode.c17 static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) in __xe_gt_apply_ccs_mode() argument
27 xe_assert(xe, num_engines && num_engines <= num_slices); in __xe_gt_apply_ccs_mode()
28 xe_assert(xe, !(num_slices % num_engines)); in __xe_gt_apply_ccs_mode()
48 for (width = num_slices / num_engines; width; width--) { in __xe_gt_apply_ccs_mode()
56 if (hwe->logical_instance >= num_engines) in __xe_gt_apply_ccs_mode()
80 mode, config, num_engines, num_slices); in __xe_gt_apply_ccs_mode()
117 u32 num_engines, num_slices; in ccs_mode_store() local
126 ret = kstrtou32(buff, 0, &num_engines); in ccs_mode_store()
135 if (!num_engines || num_engines > num_slices || num_slices % num_engines) { in ccs_mode_store()
137 num_engines, num_slices); in ccs_mode_store()
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H A Dxe_oa_types.h108 u32 num_engines; member
H A Dxe_query.c223 engines->num_engines = i; in query_engines()
645 size += gt->oa.oa_unit[i].num_engines * in calc_oa_unit_query_size()
702 du->num_engines = j; in query_oa_units()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dselftest_guc_multi_lrc.c13 static void logical_sort(struct intel_engine_cs **engines, int num_engines) in logical_sort() argument
18 for (i = 0; i < num_engines; ++i) in logical_sort()
27 sizeof(struct intel_engine_cs *) * num_engines); in logical_sort()
/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c394 unsigned num_engines; member
417 if (idx >= set->num_engines) { in set_proto_ctx_engines_balance()
419 idx, set->num_engines); in set_proto_ctx_engines_balance()
423 idx = array_index_nospec(idx, set->num_engines); in set_proto_ctx_engines_balance()
508 if (idx >= set->num_engines) { in set_proto_ctx_engines_bond()
511 idx, set->num_engines); in set_proto_ctx_engines_bond()
515 idx = array_index_nospec(idx, set->num_engines); in set_proto_ctx_engines_bond()
609 if (slot >= set->num_engines) { in set_proto_ctx_engines_parallel_submit()
611 slot, set->num_engines); in set_proto_ctx_engines_parallel_submit()
758 set.num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines); in set_proto_ctx_engines()
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H A Di915_gem_context_types.h51 unsigned int num_engines; member
H A Di915_gem_context.h213 else if (likely(idx < e->num_engines && e->engines[idx])) in i915_gem_context_get_engine()
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_hw_arbiter.c41 for_each_set_bit(i, &ae_mask, hw_data->num_engines) in adf_init_arb()
94 for (i = 0; i < hw_data->num_engines; i++) in adf_exit_arb()
H A Dadf_accel_devices.h353 u8 num_engines; member
393 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
H A Dadf_gen2_hw_data.c37 for_each_set_bit(i, &ae_mask, hw_data->num_engines) { in adf_gen2_enable_error_correction()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_ring_submission.c733 const int num_engines = in mi_set_context() local
734 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
741 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); in mi_set_context()
758 if (num_engines) { in mi_set_context()
761 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
811 if (num_engines) { in mi_set_context()
815 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
/linux/drivers/dma/idxd/
H A Ddefaults.c50 engine->group->num_engines++; in idxd_load_iaa_device_defaults()
/linux/drivers/gpu/drm/omapdrm/
H A Domap_dmm_tiler.c283 for (i = 0; i < dmm->num_engines; i++) { in omap_dmm_irq_handler()
754 REFILL_BUFFER_SIZE * omap_dmm->num_engines, in omap_dmm_remove()
836 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; in omap_dmm_probe()
841 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); in omap_dmm_probe()
877 REFILL_BUFFER_SIZE * omap_dmm->num_engines, in omap_dmm_probe()
886 omap_dmm->engines = kcalloc(omap_dmm->num_engines, in omap_dmm_probe()
893 for (i = 0; i < omap_dmm->num_engines; i++) { in omap_dmm_probe()
H A Domap_dmm_priv.h168 int num_engines; member
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c318 count = engines->num_engines; in live_parallel_switch()
1369 unsigned long idx, ndwords, dw, num_engines; in igt_ctx_readonly() local
1409 num_engines = 0; in igt_ctx_readonly()
1412 num_engines++; in igt_ctx_readonly()
1461 ndwords, num_engines); in igt_ctx_readonly()
1775 unsigned long num_engines, count; in igt_vm_isolation() local
1841 num_engines = 0; in igt_vm_isolation()
1883 num_engines++; in igt_vm_isolation()
1886 count, num_engines); in igt_vm_isolation()
/linux/drivers/crypto/intel/qat/qat_c3xxxvf/
H A Dadf_c3xxxvf_hw_data.c68 hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES; in adf_init_hw_data_c3xxxiov()
/linux/drivers/crypto/intel/qat/qat_dh895xccvf/
H A Dadf_dh895xccvf_hw_data.c68 hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES; in adf_init_hw_data_dh895xcciov()
/linux/drivers/infiniband/hw/hfi1/
H A Dsdma.c1254 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) in sdma_clean() argument
1273 for (i = 0; dd->per_sdma && i < num_engines; ++i) { in sdma_clean()
1330 size_t num_engines = chip_sdma_engines(dd); in sdma_init() local
1342 num_engines = mod_num_sdma; in sdma_init()
1350 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE); in sdma_init()
1358 num_engines, descq_cnt); in sdma_init()
1361 dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma), in sdma_init()
1378 for (this_idx = 0; this_idx < num_engines; ++this_idx) { in sdma_init()
1444 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; in sdma_init()
1465 for (this_idx = 0; this_idx < num_engines; ++this_idx) { in sdma_init()
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/linux/include/uapi/drm/
H A Dxe_drm.h268 __u32 num_engines; member
1653 __u64 num_engines; member
/linux/drivers/gpu/drm/i915/
H A Di915_perf_types.h422 u32 num_engines; member
/linux/drivers/crypto/intel/qat/qat_c3xxx/
H A Dadf_c3xxx_hw_data.c122 hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES; in adf_init_hw_data_c3xxx()
/linux/drivers/crypto/intel/qat/qat_c62x/
H A Dadf_c62x_hw_data.c124 hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES; in adf_init_hw_data_c62x()
/linux/drivers/crypto/intel/qat/qat_dh895xcc/
H A Dadf_dh895xcc_hw_data.c222 hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES; in adf_init_hw_data_dh895xcc()
/linux/drivers/accel/habanalabs/common/
H A Dcommand_submission.c2501 u32 num_engines, enum hl_engine_command command) in cs_ioctl_engines() argument
2520 if (!num_engines || num_engines > max_num_of_engines) { in cs_ioctl_engines()
2521 dev_err(hdev->dev, "Number of engines %d is invalid\n", num_engines); in cs_ioctl_engines()
2526 engines = kmalloc_array(num_engines, sizeof(u32), GFP_KERNEL); in cs_ioctl_engines()
2530 if (copy_from_user(engines, engines_arr, num_engines * sizeof(u32))) { in cs_ioctl_engines()
2536 rc = hdev->asic_funcs->set_engines(hdev, engines, num_engines, command); in cs_ioctl_engines()
2616 args->in.num_engines, args->in.engine_command); in hl_cs_ioctl()
/linux/drivers/crypto/intel/qat/qat_6xxx/
H A Dadf_6xxx_hw_data.c519 for (i = 0; i < hw_data->num_engines; i++) { in adf_gen6_init_thd2arb_map()
884 hw_data->num_engines = ADF_6XXX_MAX_ACCELENGINES; in adf_init_hw_data_6xxx()

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