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Searched refs:mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h1890 #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 macro
H A Dgc_9_1_offset.h1946 #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 macro
H A Dgc_10_1_0_offset.h3978 #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 macro
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H A Dgc_10_3_0_offset.h3789 #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX 0 macro
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