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Searched refs:mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h9869 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2 macro
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H A Ddcn_2_1_0_offset.h11777 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX global() macro
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H A Ddcn_3_0_2_offset.h11909 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX global() macro
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H A Ddcn_2_0_0_offset.h13907 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX global() macro
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H A Ddcn_3_0_0_offset.h13073 #define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX global() macro
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