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Searched refs:lio_pci_readq (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn68xx_device.c38 lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL)); in lio_cn68xx_set_dpi_regs()
48 lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i))); in lio_cn68xx_set_dpi_regs()
57 lio_pci_readq(oct, CN6XXX_DPI_CTL)); in lio_cn68xx_set_dpi_regs()
120 u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG); in lio_is_210nv()
H A Dcn66xx_device.c38 lio_pci_readq(oct, CN6XXX_CIU_SOFT_RST); in lio_cn6xxx_soft_reset()
89 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mps()
117 r64 = lio_pci_readq(oct, CN6XXX_DPI_SLI_PRTX_CFG(oct->pcie_port)); in lio_cn6xxx_setup_pcie_mrrs()
127 return ((lio_pci_readq(oct, CN6XXX_MIO_RST_BOOT) >> 24) & 0x3f) * 50; in lio_cn6xxx_coprocessor_clock()
420 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
423 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
433 bar1 = lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_setup()
445 return (u32)lio_pci_readq(oct, CN6XXX_BAR1_REG(idx, oct->pcie_port)); in lio_cn6xxx_bar1_idx_read()
H A Dcn23xx_pf_device.c49 lio_pci_readq(oct, CN23XX_RST_SOFT_RST); in cn23xx_pf_soft_reset()
107 return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50); in cn23xx_coprocessor_clock()
878 reg_adr = lio_pci_readq( in cn23xx_bar1_idx_setup()
883 reg_adr = lio_pci_readq( in cn23xx_bar1_idx_setup()
895 WRITE_ONCE(bar1, lio_pci_readq( in cn23xx_bar1_idx_setup()
907 return (u32)lio_pci_readq( in cn23xx_bar1_idx_read()
H A Docteon_device.c1342 u64 lio_pci_readq(struct octeon_device *oct, u64 addr) in lio_pci_readq() function
1372 EXPORT_SYMBOL_GPL(lio_pci_readq);
1402 lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL); in octeon_mem_access_ok()
1406 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL); in octeon_mem_access_ok()
H A Docteon_device.h718 u64 lio_pci_readq(struct octeon_device *oct, u64 addr);
H A Dlio_main.c1533 comp = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_COMP); in liquidio_ptp_adjfine()
1575 ns = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_HI); in liquidio_ptp_gettime()
1667 cfg = lio_pci_readq(oct, CN6XXX_MIO_PTP_CLOCK_CFG); in liquidio_ptp_init()
H A Dlio_ethtool.c2976 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); in cn6xxx_read_csr_reg()