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Searched refs:intel_uncore_read_fw (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.h276 * Must be used with intel_uncore_read_fw() and friends.
431 #define intel_uncore_read_fw(...) __raw_uncore_read32(__VA_ARGS__) macro
434 #define intel_uncore_posting_read_fw(...) ((void)intel_uncore_read_fw(__VA_ARGS__))
452 old = intel_uncore_read_fw(uncore, reg); in intel_uncore_rmw_fw()
475 upper = intel_uncore_read_fw(uncore, upper_reg); in intel_uncore_read64_2x32()
478 lower = intel_uncore_read_fw(uncore, lower_reg); in intel_uncore_read64_2x32()
479 upper = intel_uncore_read_fw(uncore, upper_reg); in intel_uncore_read64_2x32()
H A Dintel_pcode.c68 if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) in __snb_pcode_rw()
85 *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA); in __snb_pcode_rw()
87 *val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1); in __snb_pcode_rw()
H A Dvlv_iosf_sb.c121 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA); in vlv_sideband_rw()
H A Di915_gpu_error.c1828 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); in gt_record_global_regs()
1851 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); in gt_record_global_regs()
1858 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); in gt_record_global_regs()
H A Dintel_uncore.c2712 * (intel_uncore_read_fw(uncore, reg) & mask) == value
2734 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) in __intel_wait_for_register_fw()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_pm_debugfs.c96 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); in vlv_drpc()
123 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); in gen6_drpc()
124 gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS); in gen6_drpc()
270 mt_fwake_req = intel_uncore_read_fw(uncore, FORCEWAKE_MT); in mtl_drpc()
515 rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; in rps_boost_show()
516 rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; in rps_boost_show()
517 rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; in rps_boost_show()
518 rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; in rps_boost_show()
H A Dintel_gt_mcr.c246 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); in rw_with_mcr_steering_fw()
256 mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); in rw_with_mcr_steering_fw()
265 val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg)); in rw_with_mcr_steering_fw()
355 err = wait_for(intel_uncore_read_fw(gt->uncore, in intel_gt_mcr_lock()
709 return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any_fw()
H A Dselftest_rc6.c118 intel_uncore_read_fw(gt->uncore, GEN6_RC_STATE), in live_rc6_manual()
119 intel_uncore_read_fw(gt->uncore, GEN6_RC_CONTROL), in live_rc6_manual()
H A Dintel_rc6.c762 upper = intel_uncore_read_fw(uncore, reg); in vlv_residency_raw()
768 lower = intel_uncore_read_fw(uncore, reg); in vlv_residency_raw()
772 upper = intel_uncore_read_fw(uncore, reg); in vlv_residency_raw()
819 time_hw = intel_uncore_read_fw(uncore, reg); in intel_rc6_residency_ns()
H A Dselftest_rps.c289 if (wait_for(intel_uncore_read_fw(gt->uncore, in live_rps_clock_interval()
304 cycles_[i] = -intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI); in live_rps_clock_interval()
309 cycles_[i] += intel_uncore_read_fw(gt->uncore, GEN6_RP_CUR_UP_EI); in live_rps_clock_interval()
573 dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)); in __measure_cs_frequency()
576 dc = intel_uncore_read_fw(engine->uncore, CS_GPR(0)) - dc; in __measure_cs_frequency()
H A Dintel_reset.c435 if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) { in gen11_lock_sfc()
449 if (!(intel_uncore_read_fw(uncore, in gen11_lock_sfc()
489 lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & in gen11_lock_sfc()
573 ack = intel_uncore_read_fw(uncore, reg); in gen8_engine_reset_prepare()
599 intel_uncore_read_fw(uncore, reg)); in gen8_engine_reset_prepare()
H A Dintel_ggtt.c197 intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6); in gen6_ggtt_invalidate()
H A Dintel_rps.c2132 freq = take_fw ? intel_uncore_read(uncore, r) : intel_uncore_read_fw(uncore, r); in __read_cagf()
/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c194 intel_uncore_read_fw(uncore, offset); in load_render_mocs()
202 intel_uncore_read_fw(uncore, offset); in load_render_mocs()
396 if (wait_for_atomic(intel_uncore_read_fw(uncore, reg) == 0, 50)) in handle_tlb_pending_event()
508 intel_uncore_read_fw(uncore, mmio->reg); in switch_mmio()
515 intel_uncore_read_fw(uncore, mmio->reg); in switch_mmio()
/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h136 static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore, in intel_uncore_read_fw() function
/linux/drivers/gpu/drm/i915/display/
H A Dintel_de.h204 val = intel_uncore_read_fw(__to_uncore(display), reg); in intel_de_read_fw()
/linux/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c790 edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP); in intel_dram_edram_detect()