/linux/drivers/md/dm-vdo/ |
H A D | encodings.c | 369 size_t initial_offset; in decode_block_map_state_2_0() local 380 initial_offset = *offset; in decode_block_map_state_2_0() 400 result = VDO_ASSERT(VDO_BLOCK_MAP_HEADER_2_0.size == *offset - initial_offset, in decode_block_map_state_2_0() 418 size_t initial_offset; in encode_block_map_state_2_0() local 422 initial_offset = *offset; in encode_block_map_state_2_0() 428 VDO_ASSERT_LOG_ONLY(VDO_BLOCK_MAP_HEADER_2_0.size == *offset - initial_offset, in encode_block_map_state_2_0() 471 size_t initial_offset; in encode_recovery_journal_state_7_0() local 475 initial_offset = *offset; in encode_recovery_journal_state_7_0() 480 VDO_ASSERT_LOG_ONLY(VDO_RECOVERY_JOURNAL_HEADER_7_0.size == *offset - initial_offset, in encode_recovery_journal_state_7_0() 496 size_t initial_offset; in decode_recovery_journal_state_7_0() local 551 size_t initial_offset; encode_slab_depot_state_2_0() local 581 size_t initial_offset; decode_slab_depot_state_2_0() local 966 size_t initial_offset; encode_layout() local 1001 size_t initial_offset; decode_layout() local [all...] |
/linux/drivers/gpu/drm/display/ |
H A D | drm_dsc_helper.c | 206 pps_payload->initial_offset = in drm_dsc_pps_payload_pack() 207 cpu_to_be16(dsc_cfg->initial_offset); in drm_dsc_pps_payload_pack() 335 u16 initial_offset; member 1279 vdsc_cfg->initial_offset = rc_params->initial_offset; in drm_dsc_setup_rc_params() 1399 vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters() 1428 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters() 1462 return 8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset); in drm_dsc_initial_scale_value() 1500 cfg->initial_offset, cfg->final_offset, cfg->slice_bpg_offset); in drm_dsc_dump_config_main_params()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/ |
H A D | rc_calc_dpi.c | 52 to->initial_offset = from->initial_offset; in copy_pps_fields() 77 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
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/linux/drivers/media/test-drivers/vidtv/ |
H A D | vidtv_mux.c | 158 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_push_si() local 214 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_push_si() 285 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_packetize_access_units() local 318 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_packetize_access_units() 356 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_pad_with_nulls() local 370 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_pad_with_nulls()
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/linux/net/xfrm/ |
H A D | xfrm_iptfs.c | 311 * @initial_offset: the value passed in to skb_prepare_frag_walk() 320 u32 initial_offset; member 328 * @initial_offset: start the walk @initial_offset into the skb. 332 * least @initial_offset large. 334 static void iptfs_skb_prepare_frag_walk(struct sk_buff *skb, u32 initial_offset, in iptfs_skb_prepare_frag_walk() argument 341 walk->initial_offset = initial_offset; in iptfs_skb_prepare_frag_walk() 349 if (initial_offset >= skb_headlen(skb)) { in iptfs_skb_prepare_frag_walk() 350 initial_offset in iptfs_skb_prepare_frag_walk() [all...] |
/linux/include/drm/display/ |
H A D | drm_dsc.h | 167 * @initial_offset: Value to use for RC model offset at slice start 169 u16 initial_offset; member 439 * @initial_offset: 442 __be16 initial_offset; member
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/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_vdsc_regs.h | 153 #define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \ argument 154 initial_offset)
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H A D | intel_display.c | 5406 PIPE_CONF_CHECK_I(dsc.config.initial_offset); in intel_pipe_config_compare()
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/linux/drivers/nvdimm/ |
H A D | btt_devs.c | 280 nd_btt->initial_offset = 0; in nd_btt_version() 295 nd_btt->initial_offset = SZ_4K; in nd_btt_version()
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H A D | btt.c | 36 return offset + nd_btt->initial_offset; in adjust_initial_offset() 1672 rawsize = size - nd_btt->initial_offset; in nvdimm_namespace_attach_btt() 1676 ARENA_MIN_SIZE + nd_btt->initial_offset); in nvdimm_namespace_attach_btt()
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H A D | nd.h | 456 int initial_offset; member
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/linux/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_dsc.c | 107 data = dsc->initial_offset << 16; in dpu_hw_dsc_config()
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H A D | dpu_hw_dsc_1_2.c | 193 data = (dsc->initial_offset & 0xffff) | in dpu_hw_dsc_config_1_2()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
H A D | dcn20_dsc.c | 308 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); in dsc_log_pps() 548 reg_vals->pps.initial_offset = 6144; in dsc_init_reg_values() 671 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
H A D | dcn401_dsc.c | 293 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()
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