1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include "display/i9xx_plane_regs.h"
29 #include "display/intel_display.h"
30 #include "display/intel_display_core.h"
31
32 #include "gt/intel_engine_regs.h"
33 #include "gt/intel_gt.h"
34 #include "gt/intel_gt_mcr.h"
35 #include "gt/intel_gt_regs.h"
36
37 #include "i915_drv.h"
38 #include "i915_reg.h"
39 #include "intel_clock_gating.h"
40 #include "intel_mchbar_regs.h"
41 #include "vlv_iosf_sb.h"
42
43 struct drm_i915_clock_gating_funcs {
44 void (*init_clock_gating)(struct drm_i915_private *i915);
45 };
46
gen9_init_clock_gating(struct drm_i915_private * i915)47 static void gen9_init_clock_gating(struct drm_i915_private *i915)
48 {
49 if (HAS_LLC(i915)) {
50 /*
51 * WaCompressedResourceDisplayNewHashMode:skl,kbl
52 * Display WA #0390: skl,kbl
53 *
54 * Must match Sampler, Pixel Back End, and Media. See
55 * WaCompressedResourceSamplerPbeMediaNewHashMode.
56 */
57 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
58 }
59
60 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
61 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
62
63 /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
64 intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
65
66 /*
67 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
68 * Display WA #0859: skl,bxt,kbl,glk,cfl
69 */
70 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
71 }
72
bxt_init_clock_gating(struct drm_i915_private * i915)73 static void bxt_init_clock_gating(struct drm_i915_private *i915)
74 {
75 gen9_init_clock_gating(i915);
76
77 /* WaDisableSDEUnitClockGating:bxt */
78 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
79
80 /*
81 * FIXME:
82 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
83 */
84 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
85
86 /*
87 * Wa: Backlight PWM may stop in the asserted state, causing backlight
88 * to stay fully on.
89 */
90 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
91 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
92 PWM1_GATING_DIS | PWM2_GATING_DIS);
93
94 /*
95 * Lower the display internal timeout.
96 * This is needed to avoid any hard hangs when DSI port PLL
97 * is off and a MMIO access is attempted by any privilege
98 * application, using batch buffers or any other means.
99 */
100 intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
101
102 /*
103 * WaFbcTurnOffFbcWatermark:bxt
104 * Display WA #0562: bxt
105 */
106 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
107 }
108
glk_init_clock_gating(struct drm_i915_private * i915)109 static void glk_init_clock_gating(struct drm_i915_private *i915)
110 {
111 gen9_init_clock_gating(i915);
112
113 /*
114 * WaDisablePWMClockGating:glk
115 * Backlight PWM may stop in the asserted state, causing backlight
116 * to stay fully on.
117 */
118 intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
119 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
120 PWM1_GATING_DIS | PWM2_GATING_DIS);
121 }
122
ibx_init_clock_gating(struct drm_i915_private * i915)123 static void ibx_init_clock_gating(struct drm_i915_private *i915)
124 {
125 /*
126 * On Ibex Peak and Cougar Point, we need to disable clock
127 * gating for the panel power sequencer or it will fail to
128 * start up when no ports are active.
129 */
130 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
131 }
132
g4x_disable_trickle_feed(struct drm_i915_private * dev_priv)133 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
134 {
135 enum pipe pipe;
136
137 for_each_pipe(dev_priv, pipe) {
138 intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe),
139 0, DISP_TRICKLE_FEED_DISABLE);
140
141 intel_uncore_rmw(&dev_priv->uncore, DSPSURF(dev_priv, pipe),
142 0, 0);
143 intel_uncore_posting_read(&dev_priv->uncore,
144 DSPSURF(dev_priv, pipe));
145 }
146 }
147
ilk_init_clock_gating(struct drm_i915_private * i915)148 static void ilk_init_clock_gating(struct drm_i915_private *i915)
149 {
150 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
151
152 /*
153 * Required for FBC
154 * WaFbcDisableDpfcClockGating:ilk
155 */
156 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
157 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
158 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
159
160 intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
161 MARIUNIT_CLOCK_GATE_DISABLE |
162 SVSMUNIT_CLOCK_GATE_DISABLE);
163 intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
164 VFMUNIT_CLOCK_GATE_DISABLE);
165
166 /*
167 * According to the spec the following bits should be set in
168 * order to enable memory self-refresh
169 * The bit 22/21 of 0x42004
170 * The bit 5 of 0x42020
171 * The bit 15 of 0x45000
172 */
173 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
174 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
175 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
176 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
177 intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
178 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
179 DISP_FBC_WM_DIS));
180
181 /*
182 * Based on the document from hardware guys the following bits
183 * should be set unconditionally in order to enable FBC.
184 * The bit 22 of 0x42000
185 * The bit 22 of 0x42004
186 * The bit 7,8,9 of 0x42020.
187 */
188 if (IS_IRONLAKE_M(i915)) {
189 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
190 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
191 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
192 }
193
194 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
195
196 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
197
198 g4x_disable_trickle_feed(i915);
199
200 ibx_init_clock_gating(i915);
201 }
202
cpt_init_clock_gating(struct drm_i915_private * i915)203 static void cpt_init_clock_gating(struct drm_i915_private *i915)
204 {
205 struct intel_display *display = i915->display;
206 enum pipe pipe;
207 u32 val;
208
209 /*
210 * On Ibex Peak and Cougar Point, we need to disable clock
211 * gating for the panel power sequencer or it will fail to
212 * start up when no ports are active.
213 */
214 intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
215 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
216 PCH_CPUNIT_CLOCK_GATE_DISABLE);
217 intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
218 /* The below fixes the weird display corruption, a few pixels shifted
219 * downward, on (only) LVDS of some HP laptops with IVY.
220 */
221 for_each_pipe(i915, pipe) {
222 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
223 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
224 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
225 if (display->vbt.fdi_rx_polarity_inverted)
226 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
227 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
228 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
229 intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
230 }
231 /* WADP0ClockGatingDisable */
232 for_each_pipe(i915, pipe) {
233 intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
234 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
235 }
236 }
237
gen6_check_mch_setup(struct drm_i915_private * i915)238 static void gen6_check_mch_setup(struct drm_i915_private *i915)
239 {
240 u32 tmp;
241
242 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD);
243 if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)
244 drm_dbg_kms(&i915->drm,
245 "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
246 tmp);
247 }
248
gen6_init_clock_gating(struct drm_i915_private * i915)249 static void gen6_init_clock_gating(struct drm_i915_private *i915)
250 {
251 u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
252
253 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
254
255 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
256
257 intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
258 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
259 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
260 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
261
262 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
263 * gating disable must be set. Failure to set it results in
264 * flickering pixels due to Z write ordering failures after
265 * some amount of runtime in the Mesa "fire" demo, and Unigine
266 * Sanctuary and Tropics, and apparently anything else with
267 * alpha test or pixel discard.
268 *
269 * According to the spec, bit 11 (RCCUNIT) must also be set,
270 * but we didn't debug actual testcases to find it out.
271 *
272 * WaDisableRCCUnitClockGating:snb
273 * WaDisableRCPBUnitClockGating:snb
274 */
275 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
276 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
277 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
278
279 /*
280 * According to the spec the following bits should be
281 * set in order to enable memory self-refresh and fbc:
282 * The bit21 and bit22 of 0x42000
283 * The bit21 and bit22 of 0x42004
284 * The bit5 and bit7 of 0x42020
285 * The bit14 of 0x70180
286 * The bit14 of 0x71180
287 *
288 * WaFbcAsynchFlipDisableFbcQueue:snb
289 */
290 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
291 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
292 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
293 intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
294 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
295 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
296 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
297 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
298 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
299 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
300
301 g4x_disable_trickle_feed(i915);
302
303 cpt_init_clock_gating(i915);
304
305 gen6_check_mch_setup(i915);
306 }
307
lpt_init_clock_gating(struct drm_i915_private * i915)308 static void lpt_init_clock_gating(struct drm_i915_private *i915)
309 {
310 /*
311 * TODO: this bit should only be enabled when really needed, then
312 * disabled when not needed anymore in order to save power.
313 */
314 if (HAS_PCH_LPT_LP(i915))
315 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
316 0, PCH_LP_PARTITION_LEVEL_DISABLE);
317
318 /* WADPOClockGatingDisable:hsw */
319 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
320 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
321 }
322
gen8_set_l3sqc_credits(struct drm_i915_private * i915,int general_prio_credits,int high_prio_credits)323 static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
324 int general_prio_credits,
325 int high_prio_credits)
326 {
327 u32 misccpctl;
328 u32 val;
329
330 /* WaTempDisableDOPClkGating:bdw */
331 misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
332 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
333
334 val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
335 val &= ~L3_PRIO_CREDITS_MASK;
336 val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
337 val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
338 intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val);
339
340 /*
341 * Wait at least 100 clocks before re-enabling clock gating.
342 * See the definition of L3SQCREG1 in BSpec.
343 */
344 intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
345 udelay(1);
346 intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
347 }
348
dg2_init_clock_gating(struct drm_i915_private * i915)349 static void dg2_init_clock_gating(struct drm_i915_private *i915)
350 {
351 /* Wa_22010954014:dg2 */
352 intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0,
353 SGSI_SIDECLK_DIS);
354 }
355
cnp_init_clock_gating(struct drm_i915_private * i915)356 static void cnp_init_clock_gating(struct drm_i915_private *i915)
357 {
358 if (!HAS_PCH_CNP(i915))
359 return;
360
361 /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
362 intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
363 }
364
cfl_init_clock_gating(struct drm_i915_private * i915)365 static void cfl_init_clock_gating(struct drm_i915_private *i915)
366 {
367 cnp_init_clock_gating(i915);
368 gen9_init_clock_gating(i915);
369
370 /* WAC6entrylatency:cfl */
371 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
372
373 /*
374 * WaFbcTurnOffFbcWatermark:cfl
375 * Display WA #0562: cfl
376 */
377 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
378 }
379
kbl_init_clock_gating(struct drm_i915_private * i915)380 static void kbl_init_clock_gating(struct drm_i915_private *i915)
381 {
382 gen9_init_clock_gating(i915);
383
384 /* WAC6entrylatency:kbl */
385 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
386
387 /* WaDisableSDEUnitClockGating:kbl */
388 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0))
389 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
390 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
391
392 /* WaDisableGamClockGating:kbl */
393 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0))
394 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
395 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
396
397 /*
398 * WaFbcTurnOffFbcWatermark:kbl
399 * Display WA #0562: kbl
400 */
401 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
402 }
403
skl_init_clock_gating(struct drm_i915_private * i915)404 static void skl_init_clock_gating(struct drm_i915_private *i915)
405 {
406 gen9_init_clock_gating(i915);
407
408 /* WaDisableDopClockGating:skl */
409 intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
410 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
411
412 /* WAC6entrylatency:skl */
413 intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
414
415 /*
416 * WaFbcTurnOffFbcWatermark:skl
417 * Display WA #0562: skl
418 */
419 intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
420 }
421
bdw_init_clock_gating(struct drm_i915_private * i915)422 static void bdw_init_clock_gating(struct drm_i915_private *i915)
423 {
424 enum pipe pipe;
425
426 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
427 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
428
429 /* WaSwitchSolVfFArbitrationPriority:bdw */
430 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
431
432 /* WaPsrDPAMaskVBlankInSRD:bdw */
433 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
434
435 for_each_pipe(i915, pipe) {
436 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
437 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
438 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
439 }
440
441 /* WaVSRefCountFullforceMissDisable:bdw */
442 /* WaDSRefCountFullforceMissDisable:bdw */
443 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
444 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
445
446 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
447 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
448
449 /* WaDisableSDEUnitClockGating:bdw */
450 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
451
452 /* WaProgramL3SqcReg1Default:bdw */
453 gen8_set_l3sqc_credits(i915, 30, 2);
454
455 /* WaKVMNotificationOnConfigChange:bdw */
456 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
457 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
458
459 lpt_init_clock_gating(i915);
460
461 /* WaDisableDopClockGating:bdw
462 *
463 * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
464 * clock gating.
465 */
466 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
467 }
468
hsw_init_clock_gating(struct drm_i915_private * i915)469 static void hsw_init_clock_gating(struct drm_i915_private *i915)
470 {
471 enum pipe pipe;
472
473 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
474 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
475
476 /* WaPsrDPAMaskVBlankInSRD:hsw */
477 intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
478
479 for_each_pipe(i915, pipe) {
480 /* WaPsrDPRSUnmaskVBlankInSRD:hsw */
481 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
482 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
483 }
484
485 /* This is required by WaCatErrorRejectionIssue:hsw */
486 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
487 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
488
489 /* WaSwitchSolVfFArbitrationPriority:hsw */
490 intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
491
492 lpt_init_clock_gating(i915);
493 }
494
ivb_init_clock_gating(struct drm_i915_private * i915)495 static void ivb_init_clock_gating(struct drm_i915_private *i915)
496 {
497 intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
498
499 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
500 intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
501
502 /* WaDisableBackToBackFlipFix:ivb */
503 intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
504 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
505 CHICKEN3_DGMG_DONE_FIX_DISABLE);
506
507 if (INTEL_INFO(i915)->gt == 1)
508 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
509 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
510 else {
511 /* must write both registers */
512 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
513 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
514 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2,
515 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
516 }
517
518 /*
519 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
520 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
521 */
522 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
523 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
524
525 /* This is required by WaCatErrorRejectionIssue:ivb */
526 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
527 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
528
529 g4x_disable_trickle_feed(i915);
530
531 intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
532 GEN6_MBC_SNPCR_MED);
533
534 if (!HAS_PCH_NOP(i915))
535 cpt_init_clock_gating(i915);
536
537 gen6_check_mch_setup(i915);
538 }
539
vlv_init_clock_gating(struct drm_i915_private * i915)540 static void vlv_init_clock_gating(struct drm_i915_private *i915)
541 {
542 /* WaDisableBackToBackFlipFix:vlv */
543 intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
544 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
545 CHICKEN3_DGMG_DONE_FIX_DISABLE);
546
547 /* WaDisableDopClockGating:vlv */
548 intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
549 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
550
551 /* This is required by WaCatErrorRejectionIssue:vlv */
552 intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
553 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
554
555 /*
556 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
557 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
558 */
559 intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
560 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
561
562 /* WaDisableL3Bank2xClockGate:vlv
563 * Disabling L3 clock gating- MMIO 940c[25] = 1
564 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
565 intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
566
567 /*
568 * WaDisableVLVClockGating_VBIIssue:vlv
569 * Disable clock gating on th GCFG unit to prevent a delay
570 * in the reporting of vblank events.
571 */
572 intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
573 }
574
chv_init_clock_gating(struct drm_i915_private * i915)575 static void chv_init_clock_gating(struct drm_i915_private *i915)
576 {
577 /* WaVSRefCountFullforceMissDisable:chv */
578 /* WaDSRefCountFullforceMissDisable:chv */
579 intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
580 GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
581
582 /* WaDisableSemaphoreAndSyncFlipWait:chv */
583 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
584 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
585
586 /* WaDisableCSUnitClockGating:chv */
587 intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
588
589 /* WaDisableSDEUnitClockGating:chv */
590 intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
591
592 /*
593 * WaProgramL3SqcReg1Default:chv
594 * See gfxspecs/Related Documents/Performance Guide/
595 * LSQC Setting Recommendations.
596 */
597 gen8_set_l3sqc_credits(i915, 38, 2);
598 }
599
g4x_init_clock_gating(struct drm_i915_private * i915)600 static void g4x_init_clock_gating(struct drm_i915_private *i915)
601 {
602 u32 dspclk_gate;
603
604 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
605 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
606 GS_UNIT_CLOCK_GATE_DISABLE |
607 CL_UNIT_CLOCK_GATE_DISABLE);
608 intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
609 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
610 OVRUNIT_CLOCK_GATE_DISABLE |
611 OVCUNIT_CLOCK_GATE_DISABLE;
612 if (IS_GM45(i915))
613 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
614 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate);
615
616 g4x_disable_trickle_feed(i915);
617 }
618
i965gm_init_clock_gating(struct drm_i915_private * i915)619 static void i965gm_init_clock_gating(struct drm_i915_private *i915)
620 {
621 struct intel_uncore *uncore = &i915->uncore;
622
623 intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
624 intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
625 intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0);
626 intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
627 intel_uncore_write16(uncore, DEUC, 0);
628 intel_uncore_write(uncore,
629 MI_ARB_STATE,
630 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
631 }
632
i965g_init_clock_gating(struct drm_i915_private * i915)633 static void i965g_init_clock_gating(struct drm_i915_private *i915)
634 {
635 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
636 I965_RCC_CLOCK_GATE_DISABLE |
637 I965_RCPB_CLOCK_GATE_DISABLE |
638 I965_ISC_CLOCK_GATE_DISABLE |
639 I965_FBC_CLOCK_GATE_DISABLE);
640 intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0);
641 intel_uncore_write(&i915->uncore, MI_ARB_STATE,
642 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
643 }
644
gen3_init_clock_gating(struct drm_i915_private * i915)645 static void gen3_init_clock_gating(struct drm_i915_private *i915)
646 {
647 u32 dstate = intel_uncore_read(&i915->uncore, D_STATE);
648
649 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
650 DSTATE_DOT_CLOCK_GATING;
651 intel_uncore_write(&i915->uncore, D_STATE, dstate);
652
653 if (IS_PINEVIEW(i915))
654 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
655 _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
656
657 /* IIR "flip pending" means done if this bit is set */
658 intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
659 _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
660
661 /* interrupts should cause a wake up from C3 */
662 intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
663
664 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
665 intel_uncore_write(&i915->uncore, MI_ARB_STATE,
666 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
667
668 intel_uncore_write(&i915->uncore, MI_ARB_STATE,
669 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
670 }
671
i85x_init_clock_gating(struct drm_i915_private * i915)672 static void i85x_init_clock_gating(struct drm_i915_private *i915)
673 {
674 intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
675
676 /* interrupts should cause a wake up from C3 */
677 intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
678 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
679
680 intel_uncore_write(&i915->uncore, MEM_MODE,
681 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
682
683 /*
684 * Have FBC ignore 3D activity since we use software
685 * render tracking, and otherwise a pure 3D workload
686 * (even if it just renders a single frame and then does
687 * absolutely nothing) would not allow FBC to recompress
688 * until a 2D blit occurs.
689 */
690 intel_uncore_write(&i915->uncore, SCPD0,
691 _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
692 }
693
i830_init_clock_gating(struct drm_i915_private * i915)694 static void i830_init_clock_gating(struct drm_i915_private *i915)
695 {
696 intel_uncore_write(&i915->uncore, MEM_MODE,
697 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
698 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
699 }
700
intel_clock_gating_init(struct drm_i915_private * i915)701 void intel_clock_gating_init(struct drm_i915_private *i915)
702 {
703 i915->clock_gating_funcs->init_clock_gating(i915);
704 }
705
nop_init_clock_gating(struct drm_i915_private * i915)706 static void nop_init_clock_gating(struct drm_i915_private *i915)
707 {
708 drm_dbg_kms(&i915->drm,
709 "No clock gating settings or workarounds applied.\n");
710 }
711
712 #define CG_FUNCS(platform) \
713 static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \
714 .init_clock_gating = platform##_init_clock_gating, \
715 }
716
717 CG_FUNCS(dg2);
718 CG_FUNCS(cfl);
719 CG_FUNCS(skl);
720 CG_FUNCS(kbl);
721 CG_FUNCS(bxt);
722 CG_FUNCS(glk);
723 CG_FUNCS(bdw);
724 CG_FUNCS(chv);
725 CG_FUNCS(hsw);
726 CG_FUNCS(ivb);
727 CG_FUNCS(vlv);
728 CG_FUNCS(gen6);
729 CG_FUNCS(ilk);
730 CG_FUNCS(g4x);
731 CG_FUNCS(i965gm);
732 CG_FUNCS(i965g);
733 CG_FUNCS(gen3);
734 CG_FUNCS(i85x);
735 CG_FUNCS(i830);
736 CG_FUNCS(nop);
737 #undef CG_FUNCS
738
739 /**
740 * intel_clock_gating_hooks_init - setup the clock gating hooks
741 * @i915: device private
742 *
743 * Setup the hooks that configure which clocks of a given platform can be
744 * gated and also apply various GT and display specific workarounds for these
745 * platforms. Note that some GT specific workarounds are applied separately
746 * when GPU contexts or batchbuffers start their execution.
747 */
intel_clock_gating_hooks_init(struct drm_i915_private * i915)748 void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
749 {
750 if (IS_DG2(i915))
751 i915->clock_gating_funcs = &dg2_clock_gating_funcs;
752 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
753 i915->clock_gating_funcs = &cfl_clock_gating_funcs;
754 else if (IS_SKYLAKE(i915))
755 i915->clock_gating_funcs = &skl_clock_gating_funcs;
756 else if (IS_KABYLAKE(i915))
757 i915->clock_gating_funcs = &kbl_clock_gating_funcs;
758 else if (IS_BROXTON(i915))
759 i915->clock_gating_funcs = &bxt_clock_gating_funcs;
760 else if (IS_GEMINILAKE(i915))
761 i915->clock_gating_funcs = &glk_clock_gating_funcs;
762 else if (IS_BROADWELL(i915))
763 i915->clock_gating_funcs = &bdw_clock_gating_funcs;
764 else if (IS_CHERRYVIEW(i915))
765 i915->clock_gating_funcs = &chv_clock_gating_funcs;
766 else if (IS_HASWELL(i915))
767 i915->clock_gating_funcs = &hsw_clock_gating_funcs;
768 else if (IS_IVYBRIDGE(i915))
769 i915->clock_gating_funcs = &ivb_clock_gating_funcs;
770 else if (IS_VALLEYVIEW(i915))
771 i915->clock_gating_funcs = &vlv_clock_gating_funcs;
772 else if (GRAPHICS_VER(i915) == 6)
773 i915->clock_gating_funcs = &gen6_clock_gating_funcs;
774 else if (GRAPHICS_VER(i915) == 5)
775 i915->clock_gating_funcs = &ilk_clock_gating_funcs;
776 else if (IS_G4X(i915))
777 i915->clock_gating_funcs = &g4x_clock_gating_funcs;
778 else if (IS_I965GM(i915))
779 i915->clock_gating_funcs = &i965gm_clock_gating_funcs;
780 else if (IS_I965G(i915))
781 i915->clock_gating_funcs = &i965g_clock_gating_funcs;
782 else if (GRAPHICS_VER(i915) == 3)
783 i915->clock_gating_funcs = &gen3_clock_gating_funcs;
784 else if (IS_I85X(i915) || IS_I865G(i915))
785 i915->clock_gating_funcs = &i85x_clock_gating_funcs;
786 else if (GRAPHICS_VER(i915) == 2)
787 i915->clock_gating_funcs = &i830_clock_gating_funcs;
788 else
789 i915->clock_gating_funcs = &nop_clock_gating_funcs;
790 }
791