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Searched refs:cp_hqd_pq_control (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c124 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in init_mqd()
125 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
189 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
190 m->cp_hqd_pq_control |= in update_mqd()
192 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
230 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
299 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v10.c110 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in init_mqd()
111 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
172 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
173 m->cp_hqd_pq_control |= in update_mqd()
176 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
214 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
320 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_cik.c179 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in __update_mqd()
183 m->cp_hqd_pq_control |= PQ_ATC_EN; in __update_mqd()
191 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in __update_mqd()
201 m->cp_hqd_pq_control |= NO_UPDATE_RPTR; in __update_mqd()
342 m->cp_hqd_pq_control = DEFAULT_RPTR_BLOCK_SIZE | in update_mqd_hiq()
351 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd_hiq()
H A Dkfd_mqd_manager_v11.c157 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in init_mqd()
158 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
226 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
227 m->cp_hqd_pq_control |= in update_mqd()
229 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
267 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
373 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
H A Dkfd_mqd_manager_v9.c186 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; in init_mqd()
187 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; in init_mqd()
251 m->cp_hqd_pq_control &= ~CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK; in update_mqd()
252 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; in update_mqd()
253 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); in update_mqd()
297 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in update_mqd()
451 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | in init_mqd_hiq()
576 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | in init_mqd_hiq_v9_4_3()
585 m->cp_hqd_pq_control in init_mqd_hiq_v9_4_3()
[all...]
/linux/drivers/gpu/drm/amd/include/
H A Dcik_structs.h96 uint32_t cp_hqd_pq_control; member
H A Dvi_structs.h305 uint32_t cp_hqd_pq_control; member
H A Dv9_structs.h315 uint32_t cp_hqd_pq_control; member
H A Dv12_structs.h820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) member
H A Dv11_structs.h820 uint32_t cp_hqd_pq_control; // offset: 145 (0x91) member
H A Dv10_structs.h821 uint32_t cp_hqd_pq_control; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2862 mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL); in gfx_v7_0_mqd_init()
2863 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2867 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2869 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2872 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
2875 mqd->cp_hqd_pq_control &= in gfx_v7_0_mqd_init()
2879 mqd->cp_hqd_pq_control |= in gfx_v7_0_mqd_init()
H A Damdgpu_amdkfd_gc_9_4_3.c329 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_4_3_hqd_load()
H A Damdgpu_amdkfd_gfx_v10_3.c240 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c225 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in hqd_load_v11()
H A Dmes_v11_0.c1141 mqd->cp_hqd_pq_control = tmp; in mes_v11_0_mqd_init()
1216 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
H A Dmes_v12_0.c1223 mqd->cp_hqd_pq_control = tmp; in mes_v12_0_mqd_init()
1305 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v12_0_queue_init_register()
H A Damdgpu_amdkfd_gfx_v10.c254 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_hqd_load()
H A Damdgpu_amdkfd_gfx_v9.c268 2 << REG_GET_FIELD(m->cp_hqd_pq_control, in kgd_gfx_v9_hqd_load()
H A Dgfx_v9_4_3.c1912 mqd->cp_hqd_pq_control = tmp; in gfx_v9_4_3_xcc_mqd_init()
2013 mqd->cp_hqd_pq_control); in gfx_v9_4_3_xcc_kiq_init_register()
2119 * check mqd->cp_hqd_pq_control since this value should not be 0 in gfx_v9_4_3_xcc_kiq_init_queue()
2122 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { in gfx_v9_4_3_xcc_kiq_init_queue()
2162 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control in gfx_v9_4_3_xcc_kcq_init_queue()
2167 if (!restore && (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_4_3_xcc_kcq_init_queue()
H A Dgfx_v9_0.c3633 mqd->cp_hqd_pq_control = tmp; in gfx_v9_0_mqd_init()
3733 mqd->cp_hqd_pq_control); in gfx_v9_0_kiq_init_register()
3839 * check mqd->cp_hqd_pq_control since this value should not be 0 in gfx_v9_0_kiq_init_queue()
3842 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control){ in gfx_v9_0_kiq_init_queue()
3883 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control in gfx_v9_0_kcq_init_queue()
3888 if (!restore && (!tmp_mqd->cp_hqd_pq_control || in gfx_v9_0_kcq_init_queue()
H A Dgfx_v12_0.c3182 mqd->cp_hqd_pq_control = tmp; in gfx_v12_0_compute_mqd_init()
3303 mqd->cp_hqd_pq_control); in gfx_v12_0_kiq_init_register()
H A Dgfx_v8_0.c4459 mqd->cp_hqd_pq_control = tmp; in gfx_v8_0_mqd_init()