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Searched refs:cfg_val (Results 1 – 9 of 9) sorted by relevance

/linux/arch/x86/kernel/cpu/resctrl/
H A Dctrlmondata.c23 u32 closid, enum resctrl_conf_type t, u32 cfg_val) in resctrl_arch_update_one() argument
33 hw_dom->ctrl_val[idx] = cfg_val; in resctrl_arch_update_one()
/linux/sound/x86/
H A Dintel_hdmi_audio.c355 union aud_cfg cfg_val = {.regval = 0}; in had_init_audio_ctrl() local
367 cfg_val.regx.num_ch = channels - 2; in had_init_audio_ctrl()
369 cfg_val.regx.layout = LAYOUT0; in had_init_audio_ctrl()
371 cfg_val.regx.layout = LAYOUT1; in had_init_audio_ctrl()
374 cfg_val.regx.packet_mode = 1; in had_init_audio_ctrl()
377 cfg_val.regx.left_align = 1; in had_init_audio_ctrl()
379 cfg_val.regx.val_bit = 1; in had_init_audio_ctrl()
383 cfg_val.regx.dp_modei = 1; in had_init_audio_ctrl()
384 cfg_val.regx.set = 1; in had_init_audio_ctrl()
387 had_write_register(intelhaddata, AUD_CONFIG, cfg_val in had_init_audio_ctrl()
[all...]
/linux/drivers/pinctrl/bcm/
H A Dpinctrl-bcm281xx.c2008 u32 cfg_val, cfg_mask; in bcm281xx_pinctrl_pin_config_set() local
2011 cfg_val = 0; in bcm281xx_pinctrl_pin_config_set()
2019 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2025 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2028 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2033 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2048 __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); in bcm281xx_pinctrl_pin_config_set()
2058 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); in bcm281xx_pinctrl_pin_config_set()
/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c293 u32 cfg_val; in xvcu_pll_set_div() local
304 cfg_val = FIELD_PREP(VCU_PLL_CFG_RES, cfg->res) | in xvcu_pll_set_div()
309 xvcu_write(base, VCU_PLL_CFG, cfg_val); in xvcu_pll_set_div()
/linux/drivers/media/i2c/
H A Dtc358746.c572 static u32 tc358746_cfg_to_cnt(unsigned long cfg_val, unsigned long clk_hz, in tc358746_cfg_to_cnt() argument
575 return div64_u64((u64)cfg_val * clk_hz + time_base - 1, time_base); in tc358746_cfg_to_cnt()
578 static u32 tc358746_ps_to_cnt(unsigned long cfg_val, unsigned long clk_hz) in tc358746_ps_to_cnt() argument
580 return tc358746_cfg_to_cnt(cfg_val, clk_hz, PSEC_PER_SEC); in tc358746_ps_to_cnt()
583 static u32 tc358746_us_to_cnt(unsigned long cfg_val, unsigned long clk_hz) in tc358746_us_to_cnt() argument
585 return tc358746_cfg_to_cnt(cfg_val, clk_hz, USEC_PER_SEC); in tc358746_us_to_cnt()
/linux/drivers/tty/serial/8250/
H A D8250_exar.c848 u16 cfg_val; in cti_board_init_fpga() local
854 ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val); in cti_board_init_fpga()
858 cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT; in cti_board_init_fpga()
859 ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val); in cti_board_init_fpga()
/linux/include/linux/
H A Dresctrl.h424 u32 closid, enum resctrl_conf_type t, u32 cfg_val);
/linux/arch/loongarch/kernel/
H A Dptrace.c234 u32 cfg_val; in cfg_get() local
238 cfg_val = read_cpucfg(i++); in cfg_get()
239 r = membuf_write(&to, &cfg_val, sizeof(u32)); in cfg_get()
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c9293 u32 cfg_val; in tg3_chip_reset() local
9299 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9301 cfg_val | (1 << 15)); in tg3_chip_reset()