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Searched refs:_pcw_shift (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt7986-apmixed.c24 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ argument
32 .pcw_shift = _pcw_shift, .div_table = _div_table, \
37 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ argument
39 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
H A Dclk-mt7981-apmixed.c26 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ argument
34 .pcw_shift = _pcw_shift, .div_table = _div_table, \
39 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ argument
41 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
H A Dclk-mt8516-apmixedsys.c25 _pcw_shift, _div_table) { \ argument
39 .pcw_shift = _pcw_shift, \
45 _pcw_shift) \ argument
47 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt8167-apmixedsys.c24 _pcw_shift, _div_table) { \ argument
38 .pcw_shift = _pcw_shift, \
44 _pcw_shift) \ argument
46 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt2712-apmixedsys.c23 _tuner_en_bit, _pcw_reg, _pcw_shift, \ argument
40 .pcw_shift = _pcw_shift, \
46 _tuner_en_bit, _pcw_reg, _pcw_shift) \ argument
50 _pcw_shift, NULL)
H A Dclk-mt8183-apmixedsys.c57 _tuner_en_bit, _pcw_reg, _pcw_shift, \ argument
76 .pcw_shift = _pcw_shift, \
84 _tuner_en_bit, _pcw_reg, _pcw_shift, \ argument
89 _tuner_en_bit, _pcw_reg, _pcw_shift, \
H A Dclk-mt8173-apmixedsys.c26 _pcw_shift, _div_table) { \ argument
40 .pcw_shift = _pcw_shift, \
46 _pcw_shift) \ argument
48 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt8192-apmixedsys.c38 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ argument
57 .pcw_shift = _pcw_shift, \
66 _pcw_reg, _pcw_shift) \ argument
70 _pcw_reg, _pcw_shift, 0, 0, 0)
H A Dclk-mt7988-apmixed.c23 _pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \ argument
41 .pcw_shift = _pcw_shift, \
H A Dclk-mt8135-apmixedsys.c20 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \ argument
34 .pcw_shift = _pcw_shift, \
H A Dclk-mt7629.c25 _pcw_shift, _div_table, _parent_name) { \ argument
39 .pcw_shift = _pcw_shift, \
46 _pcw_shift) \ argument
48 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt6797.c601 _pcw_shift, _div_table) { \ argument
615 .pcw_shift = _pcw_shift, \
621 _pcw_shift) \ argument
623 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
H A Dclk-mt8195-apmixedsys.c36 _pcw_reg, _pcw_shift, _pcw_chg_reg, \ argument
55 .pcw_shift = _pcw_shift, \
H A Dclk-mt6779.c1148 _tuner_en_bit, _pcw_reg, _pcw_shift, \ argument
1167 .pcw_shift = _pcw_shift, \
1175 _tuner_en_bit, _pcw_reg, _pcw_shift, \ argument
1180 _tuner_en_bit, _pcw_reg, _pcw_shift, \
H A Dclk-mt6765.c673 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\ argument
691 .pcw_shift = _pcw_shift, \
698 _pcw_shift) \ argument
702 _pcw_reg, _pcw_shift, NULL) \