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Searched refs:RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK (Results 1 – 8 of 8) sorted by relevance

/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_sh_mask.h11501 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff macro
Ddce_11_0_sh_mask.h12609 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff macro
Ddce_10_0_sh_mask.h12603 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff macro
Ddce_11_2_sh_mask.h13225 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xffffffff macro
Ddce_12_0_sh_mask.h56074 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK … macro
/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_1_0_sh_mask.h949 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK … macro
Ddcn_3_0_0_sh_mask.h62722 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK … macro
Ddcn_2_0_0_sh_mask.h59146 #define RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK … macro