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Searched refs:GC_HWIP (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h111 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP, 0)
118 uint32_t r0 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \
119 uint32_t r1 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \
120 uint32_t spare_int = adev->reg_offset[GC_HWIP][inst][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \
139 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP, inst)
143 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP, 0)
155 uint32_t r2 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \
156 uint32_t r3 = adev->reg_offset[GC_HWIP][inst][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \
157 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \
158 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][ins
[all...]
H A Dgmc_v9_0.c659 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
669 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
793 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || in gmc_v9_0_use_invalidate_semaphore()
905 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
1136 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); in gmc_v9_0_get_coherence_flags()
1270 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3)) in gmc_v9_0_override_vm_pte_flags()
1565 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v9_0_init_nps_details()
1586 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) || in gmc_v9_0_early_init()
1587 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) || in gmc_v9_0_early_init()
1597 if (amdgpu_ip_version(adev, GC_HWIP, in gmc_v9_0_early_init()
[all...]
H A Damdgpu_ip.c34 case GC_HWIP: in amdgpu_logical_to_dev_inst()
85 { GC_HWIP, adev->gfx.xcc_mask }, in amdgpu_ip_map_init()
H A Dgmc_v10_0.c147 (amdgpu_ip_version(adev, GC_HWIP, 0) < in gmc_v10_0_process_interrupt()
281 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_gpu_tlb()
312 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_gpu_tlb()
611 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_set_gfxhub_funcs()
727 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_mc_init()
794 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
812 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v10_0_sw_init()
1115 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || in gmc_v10_0_get_clockgating_state()
1116 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) in gmc_v10_0_get_clockgating_state()
H A Damdgpu_mes.c119 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in amdgpu_mes_init()
547 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, in amdgpu_mes_init_microcode()
552 } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_init_microcode()
553 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) { in amdgpu_mes_init_microcode()
626 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
627 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
H A Damdgpu_discovery.c214 [GC_HWIP] = GC_HWID,
371 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { in amdgpu_discovery_harvest_config_quirk()
1536 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && in amdgpu_discovery_harvest_ip()
1894 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_common_ip_blocks()
1940 "Failed to add common ip block(GC_HWIP:0x%x)\n", in amdgpu_discovery_set_common_ip_blocks()
1941 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_common_ip_blocks()
1950 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_discovery_set_gmc_ip_blocks()
1995 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", in amdgpu_discovery_set_gmc_ip_blocks()
1996 amdgpu_ip_version(adev, GC_HWIP, 0)); in amdgpu_discovery_set_gmc_ip_blocks()
2251 switch (amdgpu_ip_version(adev, GC_HWIP, in amdgpu_discovery_set_gc_ip_blocks()
[all...]
H A Dgmc_v12_0.c211 GC_HWIP : MMHUB_HWIP; in gmc_v12_0_flush_vm_hub()
528 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && in gmc_v12_0_get_dcc_alignment()
529 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) in gmc_v12_0_get_dcc_alignment()
588 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_set_gfxhub_funcs()
743 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v12_0_sw_init()
H A Dgmc_v11_0.c242 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_gpu_tlb()
586 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_set_gfxhub_funcs()
650 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && in gmc_v11_0_vram_gtt_location()
752 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
760 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gmc_v11_0_sw_init()
H A Dgfx_v9_0.c1098 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_init_golden_registers()
1154 if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) && in gfx_v9_0_init_golden_registers()
1155 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2))) in gfx_v9_0_init_golden_registers()
1298 if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) && in gfx_v9_0_check_fw_write_wait()
1299 (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) && in gfx_v9_0_check_fw_write_wait()
1306 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_fw_write_wait()
1410 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 3, 0)) && in check_if_enlarge_doorbell_range()
1423 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v9_0_check_if_need_gfxoff()
1540 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) || in gfx_v9_0_load_mec2_fw_bin_support()
1541 amdgpu_ip_version(adev, GC_HWIP, in gfx_v9_0_load_mec2_fw_bin_support()
[all...]
H A Damdgpu_vm.h123 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PTE_PRT_GFX12 : AMDGPU_PTE_PRT)
137 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_BFS_GFX12(a) : AMDGPU_PDE_BFS(a))
141 ((amdgpu_ip_version((adev), GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ? AMDGPU_PDE_PTE_GFX12 : AMDGPU_PDE_PTE)
H A Ddimgrey_cavefish_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in aldebaran_reg_base_init()
H A Damdgpu_display.c796 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) in convert_tiling_flags_to_modifier()
798 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in convert_tiling_flags_to_modifier()
801 else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in convert_tiling_flags_to_modifier()
811 if (amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
818 if (amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
876 amdgpu_ip_version(adev, GC_HWIP, 0) < in convert_tiling_flags_to_modifier()
914 if ((amdgpu_ip_version(adev, GC_HWIP, in convert_tiling_flags_to_modifier()
1274 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) in amdgpu_display_framebuffer_init()
H A Darct_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
H A Dpsp_v10_0.c61 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0)) && in psp_v10_0_init_microcode()
H A Damdgpu_device.c790 GC_HWIP, false, in amdgpu_device_xcc_rreg()
921 GC_HWIP, true, in amdgpu_device_xcc_wreg()
1442 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || in amdgpu_device_asic_init()
1443 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || in amdgpu_device_asic_init()
1444 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0) || in amdgpu_device_asic_init()
1445 amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0)) { in amdgpu_device_asic_init()
1885 if (!(amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 0) || in amdgpu_device_aspm_support_quirk()
1886 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 1))) in amdgpu_device_aspm_support_quirk()
2758 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && in amdgpu_device_ip_early_init()
2787 amdgpu_ip_version((adev), GC_HWIP, in amdgpu_device_ip_early_init()
[all...]
H A Dvega10_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
H A Dimu_v11_0.c54 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v11_0_init_microcode()
363 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in imu_v11_0_program_rlc_ram()
H A Dimu_v12_0.c50 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); in imu_v12_0_init_microcode()
375 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in imu_v12_0_program_rlc_ram()
H A Dvega20_reg_init.c34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
H A Dsoc24.c262 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_need_full_reset()
388 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc24_common_early_init()
H A Damdgpu_ucode.c1336 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in amdgpu_ucode_legacy_naming()
1349 } else if (block_type == GC_HWIP) { in amdgpu_ucode_legacy_naming()
1350 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in amdgpu_ucode_legacy_naming()
1425 case GC_HWIP: in amdgpu_ucode_ip_version_decode()
H A Dsoc21.c454 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_need_full_reset()
579 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc21_common_early_init()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_int_process_v9.c170 if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { in event_interrupt_poison_consumption_v9()
177 } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { in event_interrupt_poison_consumption_v9()
H A Dkfd_device.c195 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); in kfd_device_info_set_event_interrupt_class()
313 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in kgd2kfd_probe()
474 if (amdgpu_ip_version(adev, GC_HWIP, 0)) in kgd2kfd_probe()
477 amdgpu_ip_version(adev, GC_HWIP, 0), in kgd2kfd_probe()

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