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Searched refs:CLK_TOP_MEM_SEL (Results 1 – 17 of 17) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-topckgen.h50 #define CLK_TOP_MEM_SEL 42 macro
H A Dmt8135-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
H A Dmt7629-clk.h84 #define CLK_TOP_MEM_SEL 74 macro
H A Dmt7622-clk.h69 #define CLK_TOP_MEM_SEL 57 macro
H A Dmediatek,mt6795-clk.h91 #define CLK_TOP_MEM_SEL 80 macro
H A Dmt8173-clk.h93 #define CLK_TOP_MEM_SEL 83 macro
H A Dmt6765-clk.h132 #define CLK_TOP_MEM_SEL 97 macro
H A Dmediatek,mt8365-clk.h72 #define CLK_TOP_MEM_SEL 62 macro
H A Dmt2712-clk.h131 #define CLK_TOP_MEM_SEL 100 macro
H A Dmt2701-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt7629.c464 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
572 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); in mtk_topckgen_init()
H A Dclk-mt6735-topckgen.c336 MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR, 8, 1, 0, 0),
H A Dclk-mt6795-topckgen.c454 TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
H A Dclk-mt8173-topckgen.c532 MUX_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1,
H A Dclk-mt2712.c646 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
H A Dclk-mt8365.c413 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
H A Dclk-mt6765.c372 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,