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Searched refs:AMDGPU_VCN_CONTEXT_SIZE (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c397 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_1_mc_resume()
503 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
815 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_1_start_sriov()
H A Damdgpu_vcn.h30 #define AMDGPU_VCN_CONTEXT_SIZE (512*1024) macro
H A Dvcn_v4_0_3.c508 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_mc_resume()
617 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1093 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_start_sriov()
H A Dvcn_v2_0.c433 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_mc_resume()
525 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
2052 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_0_start_sriov()
H A Dvcn_v4_0.c501 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_mc_resume()
602 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1453 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_start_sriov()
H A Dvcn_v5_0_0.c418 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v5_0_0_mc_resume()
520 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v2_5.c664 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
755 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1519 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_sriov_start()
H A Dvcn_v3_0.c570 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_mc_resume()
661 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1496 AMDGPU_VCN_CONTEXT_SIZE); in vcn_v3_0_start_sriov()
H A Dvcn_v4_0_5.c451 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_5_mc_resume()
558 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v1_0.c388 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v1_0_mc_resume_spg_mode()
463 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, in vcn_v1_0_mc_resume_dpg_mode()
H A Damdgpu_vcn.c199 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; in amdgpu_vcn_sw_init()