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/linux/drivers/pci/endpoint/
H A Dpci-epc-mem.c41 * @windows: pointer to windows supported by the device
42 * @num_windows: number of windows device supports
48 struct pci_epc_mem_window *windows, in pci_epc_multi_mem_init() argument
62 if (!windows || !num_windows) in pci_epc_multi_mem_init()
65 epc->windows = kcalloc(num_windows, sizeof(*epc->windows), GFP_KERNEL); in pci_epc_multi_mem_init()
66 if (!epc->windows) in pci_epc_multi_mem_init()
70 page_size = windows[i].page_size; in pci_epc_multi_mem_init()
74 pages = windows[ in pci_epc_multi_mem_init()
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/linux/drivers/mailbox/
H A Darm_mhuv2.c8 * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
11 * windows.
19 * hardware - mainly the number of channel windows implemented by the platform,
38 /* Maximum number of channel windows */
167 * @windows: Channel windows implemented by the platform.
182 unsigned int windows; member
222 * @windows: Total number of windows consumed by the channel, only relevant
233 u32 windows; member
352 const int windows = priv->windows; mhuv2_data_transfer_read_data() local
451 int windows = priv->windows; mhuv2_data_transfer_send_data() local
503 int channel = 0, i, j, offset = 0, windows, protocol, ch_wn; get_irq_chan_comb() local
797 int channel = 0, i, offset, doorbell, protocol, windows; mhuv2_mbox_of_xlate() local
839 int protocol, windows, channels = 0, total_windows = 0, i; mhuv2_verify_protocol() local
878 int protocol, windows = 0, next_window = 0, i, j, k; mhuv2_allocate_channels() local
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-rev2.dtsi114 num-ob-windows = <8>;
115 num-ib-windows = <8>;
124 num-ob-windows = <8>;
125 num-ib-windows = <8>;
134 num-ob-windows = <256>;
135 num-ib-windows = <24>;
144 num-ob-windows = <8>;
145 num-ib-windows = <8>;
155 num-ob-windows = <256>;
156 num-ib-windows
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H A Dimx8-ss-hsio.dtsi97 num-ib-windows = <6>;
98 num-ob-windows = <6>;
/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dcorec37d.c37 const u32 windows = 8; /*XXX*/ in corec37d_wndw_owner() local
40 if ((ret = PUSH_WAIT(push, windows * 2))) in corec37d_wndw_owner()
43 for (i = 0; i < windows; i++) { in corec37d_wndw_owner()
131 const u32 windows = 8; /*XXX*/ in corec37d_init() local
134 if ((ret = PUSH_WAIT(push, 2 + windows * 5))) in corec37d_init()
139 for (i = 0; i < windows; i++) { in corec37d_init()
H A Dcorec57d.c34 const u32 windows = 8; /*XXX*/ in corec57d_init() local
37 if ((ret = PUSH_WAIT(push, 2 + windows * 5))) in corec57d_init()
42 for (i = 0; i < windows; i++) { in corec57d_init()
H A Dcoreca7d.c61 const u32 windows = 8, heads = 4; in coreca7d_init() local
64 ret = PUSH_WAIT(push, windows * 6 + heads * 6); in coreca7d_init()
68 for (i = 0; i < windows; i++) { in coreca7d_init()
/linux/drivers/pci/controller/
H A Dpcie-iproc-bcma.c62 pci_add_resource(&bridge->windows, &pcie->mem); in iproc_bcma_pcie_probe()
63 ret = devm_request_pci_bus_resources(dev, &bridge->windows); in iproc_bcma_pcie_probe()
71 return iproc_pcie_setup(pcie, &bridge->windows); in iproc_bcma_pcie_probe()
H A Dpcie-rockchip-ep.c762 struct pci_epc_mem_window *windows = NULL; in rockchip_pcie_ep_init_ob_mem() local
771 windows = devm_kcalloc(dev, ep->max_regions, in rockchip_pcie_ep_init_ob_mem()
773 if (!windows) in rockchip_pcie_ep_init_ob_mem()
777 windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i); in rockchip_pcie_ep_init_ob_mem()
778 windows[i].size = SZ_1M; in rockchip_pcie_ep_init_ob_mem()
779 windows[i].page_size = SZ_1M; in rockchip_pcie_ep_init_ob_mem()
781 err = pci_epc_multi_mem_init(ep->epc, windows, ep->max_regions); in rockchip_pcie_ep_init_ob_mem()
782 devm_kfree(dev, windows); in rockchip_pcie_ep_init_ob_mem()
/linux/Documentation/admin-guide/media/
H A Dlmedm04.rst12 The Sharp 7395 driver can be found in windows/system32/drivers
57 only found in windows/system32/drivers
69 The Sharp 0194 tuner driver can be found in windows/system32/drivers
90 The m88rs2000 tuner driver can be found in windows/system32/drivers
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Decm.txt9 windows are configured. For ECM based devices this is the first 4k
11 number of local access windows as specified by fsl,num-laws.
31 windows for this device.
H A Dmcm.txt9 windows are configured. For MCM based devices this is the first 4k
11 number of local access windows as specified by fsl,num-laws.
31 windows for this device.
/linux/Documentation/driver-api/
H A Dvme.rst59 The driver can request ownership of one or more master windows
60 (:c:func:`vme_master_request`), slave windows (:c:func:`vme_slave_request`)
64 attributes of the driver in question. For slave windows these attributes are
66 bus cycle types required in 'cycle'. Master windows add a further set of
84 Master windows
87 Master windows provide access from the local processor[s] out onto the VME bus.
88 The number of windows available and the available access modes is dependent on
106 :c:func:`vme_master_write` used to write to configured master windows.
113 Slave windows
116 Slave windows provid
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/linux/arch/alpha/kernel/
H A Dsys_nautilus.c212 pci_add_resource(&bridge->windows, &ioport_resource); in nautilus_init_pci()
215 pci_add_resource(&bridge->windows, &irongate_mem); in nautilus_init_pci()
217 pci_add_resource(&bridge->windows, &busn_resource); in nautilus_init_pci()
/linux/arch/m68k/coldfire/
H A Dpci.c199 * Set up the initiator windows for memory and IO mapping. in mcf_pci_init()
211 * Set up the target windows for access from the PCI bus back to the in mcf_pci_init()
232 pci_add_resource(&bridge->windows, &ioport_resource); in mcf_pci_init()
233 pci_add_resource(&bridge->windows, &iomem_resource); in mcf_pci_init()
234 pci_add_resource(&bridge->windows, &busn_resource); in mcf_pci_init()
/linux/drivers/spi/
H A Dspi-aspeed-smc.c386 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS]) in aspeed_spi_get_windows()
394 windows[cs].cs = cs; in aspeed_spi_get_windows()
395 windows[cs].size = data->segment_end(aspi, reg_val) - in aspeed_spi_get_windows()
397 windows[cs].offset = data->segment_start(aspi, reg_val) - aspi->ahb_base_phy; in aspeed_spi_get_windows()
399 windows[cs].offset, windows[cs].size); in aspeed_spi_get_windows()
404 * On the AST2600, some CE windows are closed by default at reset but
410 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 }; in aspeed_spi_chip_set_default_window() local
411 struct aspeed_spi_window *win = &windows[chip->cs]; in aspeed_spi_chip_set_default_window()
418 aspeed_spi_get_windows(aspi, windows); in aspeed_spi_chip_set_default_window()
480 struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 }; aspeed_spi_chip_adjust_window() local
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/linux/Documentation/arch/powerpc/
H A Dpci_iov_resource_on_powernv.rst58 contain two "windows", depending on the value of PCI address bit 59.
63 - For MSIs, we have two windows in the address space (one at the top of
74 Like other PCI host bridges, the Power8 IODA2 PHB supports "windows"
76 window and sixteen M64 windows. They have different characteristics.
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
110 - The M64 windows:
123 * Support overlaps. If an address is covered by multiple windows,
155 We would like to investigate using additional M64 windows in "single
201 - Single segmented M64 windows: A segmented M64 window could be used just
207 - Multiple segmented M64 windows
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/linux/Documentation/devicetree/bindings/pci/
H A Dti-pci.txt52 - num-ib-windows : number of inbound address translation windows
53 - num-ob-windows : number of outbound address translation windows
/linux/drivers/pci/
H A Dhost-bridge.c58 resource_list_for_each_entry(window, &bridge->windows) { in pcibios_resource_to_bus()
83 resource_list_for_each_entry(window, &bridge->windows) { in pcibios_bus_to_resource()
/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt37 size for the address decoding windows allocated for
106 entries for translation that do not correspond to valid windows (S = 0xf)
198 The mbus-node ranges property defines a set of mbus windows that are expected
203 chooses to use a different set of mbus windows, it must ensure that any address
206 The operating system may insert additional mbus windows that do not conflict
210 is needed to set up the other windows.
/linux/drivers/ntb/hw/idt/
H A DKconfig19 with chosen valid aperture. For memory windows related BARs the
20 aperture settings shall determine the maximum size of memory windows
/linux/arch/um/drivers/
H A Dvirt-pci.c577 pci_add_resource(&bridge->windows, &virt_iomem_resource); in um_pci_init()
578 pci_add_resource(&bridge->windows, &busn_resource); in um_pci_init()
605 pci_free_resource_list(&bridge->windows); in um_pci_init()
615 pci_free_resource_list(&bridge->windows); in um_pci_exit()
/linux/Documentation/gpu/
H A Dtegra.rst86 A display controller controls a set of windows that can be used to composite
88 ordering to individual windows (by programming the corresponding blending
90 assume a fixed Z ordering of the windows (window A is the root window, that
91 is, the lowest, while windows B and C are overlaid on top of window A). The
92 overlay windows support multiple pixel formats and can automatically convert
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568-nanopi-r5s.dts126 num-ib-windows = <8>;
127 num-ob-windows = <8>;
/linux/rust/pin-init/examples/
H A Dpthread_mutex.rs8 #[cfg(not(windows))]
145 #[cfg(all(any(feature = "std", feature = "alloc"), not(windows)))] in main()

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