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Searched refs:vpll_con0 (Results 1 – 1 of 1) sorted by relevance

/linux-3.3/arch/arm/mach-exynos/
Dclock.c1368 unsigned int vpll_con0, vpll_con1 = 0; in exynos4_vpll_set_rate() local
1375 vpll_con0 = __raw_readl(S5P_VPLL_CON0); in exynos4_vpll_set_rate()
1376 vpll_con0 &= ~(0x1 << 27 | \ in exynos4_vpll_set_rate()
1388 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT; in exynos4_vpll_set_rate()
1389 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT; in exynos4_vpll_set_rate()
1390 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT; in exynos4_vpll_set_rate()
1394 vpll_con0 |= vpll_div[i][7] << 27; in exynos4_vpll_set_rate()
1405 __raw_writel(vpll_con0, S5P_VPLL_CON0); in exynos4_vpll_set_rate()