Home
last modified time | relevance | path

Searched refs:pll_ratio (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/phy/st/
H A Dphy-miphy28lp.c235 struct pll_ratio { struct
244 static struct pll_ratio sata_pll_ratio = { argument
253 static struct pll_ratio pcie_pll_ratio = {
262 static struct pll_ratio usb3_pll_ratio = {
384 struct pll_ratio *pll_ratio) in miphy28lp_pll_calibration() argument
391 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration()
394 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); in miphy28lp_pll_calibration()
395 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); in miphy28lp_pll_calibration()
396 writeb_relaxed(pll_ratio in miphy28lp_pll_calibration()
492 miphy28lp_compensation(struct miphy28lp_phy * miphy_phy,struct pll_ratio * pll_ratio) miphy28lp_compensation() argument
[all...]
/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c384 u32 pll_ratio = 0; in glk_dsi_program_esc_clock() local
391 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in glk_dsi_program_esc_clock()
393 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; in glk_dsi_program_esc_clock()
431 u32 pll_ratio = 0; in bxt_dsi_program_clocks() local
446 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in bxt_dsi_program_clocks()
447 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; in bxt_dsi_program_clocks()
/linux/sound/soc/codecs/
H A Dnau8810.c532 u64 f2, f2_max, pll_ratio; in nau8810_calc_pll() local
557 pll_ratio = div_u64(f2 << 28, pll_in); in nau8810_calc_pll()
559 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) { in nau8810_calc_pll()
560 pll_ratio <<= 1; in nau8810_calc_pll()
563 pll_param->pll_int = (pll_ratio >> 28) & 0xF; in nau8810_calc_pll()
564 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4); in nau8810_calc_pll()
H A Dnau8822.c619 u64 f2, f2_max, pll_ratio; in nau8822_calc_pll() local
644 pll_ratio = div_u64(f2 << 28, pll_in); in nau8822_calc_pll()
646 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) { in nau8822_calc_pll()
647 pll_ratio <<= 1; in nau8822_calc_pll()
650 pll_param->pll_int = (pll_ratio >> 28) & 0xF; in nau8822_calc_pll()
651 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4); in nau8822_calc_pll()
/linux/drivers/media/usb/dvb-usb/
H A Ddib0700_devices.c225 .pll_ratio = 8,
391 .pll_ratio = 8,
660 .pll_ratio = 8,
952 .pll_ratio = 20,
1178 .pll_ratio = 20,
1517 .pll_ratio = 18,
1630 u8 pll_ratio; in dib8090_compute_pll_parameters() local
1632 for (pll_ratio = 17; pll_ratio <= 20; pll_ratio in dib8090_compute_pll_parameters()
1654 u8 pll_ratio, band = BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); dib8096_set_param_override() local
[all...]
H A Dcxusb.c1075 .pll_ratio = 20,
/linux/drivers/media/dvb-frontends/
H A Ddibx000_common.h120 u8 pll_ratio; member
H A Ddib8000.c700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
730 (pll->pll_range<<12) | (pll->pll_ratio<<6) | in dib8000_reset_pll()
758 pll->pll_ratio == loopdiv)) in dib8000_update_pll()
761 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio); in dib8000_update_pll()
769 ((pll->pll_ratio & 0x3f) << 6) | in dib8000_update_pll()
776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
802 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio); in dib8000_update_pll()
807 ratio = state->cfg.pll->pll_ratio; in dib8000_update_pll()