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/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dethtool_lanes.sh30 log_test "SKIP: driver does not support lanes setting"
41 local lanes=$1; shift
48 ((chosen_lanes == lanes))
49 check_err $? "swp1 advertise $max_speed and $lanes, devs sync to $chosen_lanes"
66 ethtool -s $swp1 speed $max_speed lanes $unsupported_lanes $autoneg_str &> /dev/null
67 check_fail $? "Unsuccessful $unsupported_lanes lanes setting was expected"
94 local lanes=$1; shift
98 if [[ $speed -eq ${arr[$i]} && $lanes -eq ${arr[i+1]} ]]; then
109 local lanes
118 lanes
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j722s-evm-csi2-quad-rpi-cam-imx219.dtso114 clock-lanes = <0>;
115 data-lanes = <1 2>;
146 clock-lanes = <0>;
147 data-lanes = <1 2>;
183 clock-lanes = <0>;
184 data-lanes = <1 2>;
215 clock-lanes = <0>;
216 data-lanes = <1 2>;
235 clock-lanes = <0>;
236 data-lanes
[all...]
H A Dk3-j722s-evm-csi2-quad-tevi-ov5640.dtso111 clock-lanes = <0>;
112 data-lanes = <1 2>;
142 clock-lanes = <0>;
143 data-lanes = <1 2>;
178 clock-lanes = <0>;
179 data-lanes = <1 2>;
209 clock-lanes = <0>;
210 data-lanes = <1 2>;
229 clock-lanes = <0>;
230 data-lanes
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H A Dk3-j721e-sk-csi2-dual-imx219.dtso72 clock-lanes = <0>;
73 data-lanes = <1 2>;
96 clock-lanes = <0>;
97 data-lanes = <1 2>;
116 clock-lanes = <0>;
117 data-lanes = <1 2>;
163 clock-lanes = <0>;
164 data-lanes = <1 2>;
/linux/arch/arm64/boot/dts/renesas/
H A Dhihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi18 clock-lanes = <0>;
19 data-lanes = <1 2>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
49 clock-lanes = <0>;
50 data-lanes = <1 2>;
63 clock-lanes = <0>;
64 data-lanes = <1 2>;
H A Dr8a779a0-falcon-csi-dsi.dtsi21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
40 clock-lanes = <0>;
41 data-lanes = <1 2 3 4>;
59 clock-lanes = <0>;
60 data-lanes = <1 2 3 4>;
111 clock-lanes = <0>;
112 data-lanes = <1 2 3 4>;
132 clock-lanes = <0>;
133 data-lanes
[all...]
H A Dwhite-hawk-csi-dsi.dtsi22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
45 clock-lanes = <0>;
46 data-lanes = <1 2 3>;
93 clock-lanes = <0>;
94 data-lanes = <1 2 3>;
114 clock-lanes = <0>;
115 data-lanes = <1 2 3>;
H A Dr8a774c0-ek874-mipi-2.1.dts38 clock-lanes = <0>;
39 data-lanes = <1 2>;
52 clock-lanes = <0>;
53 data-lanes = <1 2>;
62 clock-lanes = <0>;
63 data-lanes = <1 2>;
/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c35 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
37 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
44 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
47 drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n", ret); in hibmc_dp_link_training_configure()
122 for (i = 0; i < dp->link.cap.lanes; i++) in hibmc_dp_link_training_cr_pre()
129 ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
130 if (ret != dp->link.cap.lanes) { in hibmc_dp_link_training_cr_pre()
144 for (lane = 0; lane < dp->link.cap.lanes; lane++) in hibmc_dp_link_get_adjust_train()
183 switch (dp->link.cap.lanes) { in hibmc_dp_link_reduce_lane()
185 dp->link.cap.lanes in hibmc_dp_link_reduce_lane()
[all...]
/linux/drivers/gpu/drm/tegra/
H A Ddp.c51 link->lanes = 0; in drm_dp_link_reset()
233 link->lanes = link->max_lanes; in drm_dp_link_probe()
279 values[1] = link->lanes; in drm_dp_link_configure()
314 * with the lowest number of lanes and the lowest possible link rate that can
326 /* available number of lanes */ in drm_dp_link_choose()
327 static const unsigned int lanes[3] = { 1, 2, 4 }; in drm_dp_link_choose() local
335 for (i = 0; i < ARRAY_SIZE(lanes) && lanes[i] <= link->max_lanes; i++) { in drm_dp_link_choose()
338 * Capacity for this combination of lanes and rate, in drm_dp_link_choose()
345 capacity = lanes[ in drm_dp_link_choose()
402 unsigned int lanes = link->lanes, *vs, *pe, *pc, i; drm_dp_link_apply_training() local
[all...]
/linux/drivers/media/platform/ti/omap3isp/
H A Dispcsiphy.c167 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
179 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
182 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
189 /* Clock and data lanes verification */ in omap3isp_csiphy_config()
191 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
194 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
197 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
200 if (lanes->clk.pol > 1 || lanes in omap3isp_csiphy_config()
[all...]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dport.c1042 [MLX5E_1000BASE_CX_SGMII] = {.speed = 1000, .lanes = 1},
1043 [MLX5E_1000BASE_KX] = {.speed = 1000, .lanes = 1},
1044 [MLX5E_10GBASE_CX4] = {.speed = 10000, .lanes = 4},
1045 [MLX5E_10GBASE_KX4] = {.speed = 10000, .lanes = 4},
1046 [MLX5E_10GBASE_KR] = {.speed = 10000, .lanes = 1},
1047 [MLX5E_20GBASE_KR2] = {.speed = 20000, .lanes = 2},
1048 [MLX5E_40GBASE_CR4] = {.speed = 40000, .lanes = 4},
1049 [MLX5E_40GBASE_KR4] = {.speed = 40000, .lanes = 4},
1050 [MLX5E_56GBASE_R4] = {.speed = 56000, .lanes = 4},
1051 [MLX5E_10GBASE_CR] = {.speed = 10000, .lanes
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/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c22 unsigned int lanes, in phy_mipi_dphy_calc_config() argument
33 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_calc_config()
76 cfg->lanes = lanes; in phy_mipi_dphy_calc_config()
83 unsigned int lanes, in phy_mipi_dphy_get_default_config() argument
86 return phy_mipi_dphy_calc_config(pixel_clock, bpp, lanes, 0, cfg); in phy_mipi_dphy_get_default_config()
92 unsigned int lanes, in phy_mipi_dphy_get_default_config_for_hsclk() argument
98 return phy_mipi_dphy_calc_config(0, 0, lanes, hs_clk_rate, cfg); in phy_mipi_dphy_get_default_config_for_hsclk()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_common.c18 prop = of_find_property(ep, "lanes", &len); in hdmi_parse_lanes_of()
20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
23 dev_err(&pdev->dev, "bad number of lanes\n"); in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_common.c18 prop = of_find_property(ep, "lanes", &len); in hdmi_parse_lanes_of()
20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
23 dev_err(&pdev->dev, "bad number of lanes\n"); in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
/linux/tools/testing/selftests/drivers/net/hw/
H A Ddevlink_port_split.py12 # Test port split configuration using devlink-port lanes attribute.
77 Get the $port's maximum number of lanes.
78 Return: number of lanes, e.g. 1, 2, 4 and 8.
86 if 'lanes' in values:
87 lanes = values['lanes']
89 lanes = 0
90 return lanes
150 def exists_and_lanes(ports, lanes, dev): argument
153 $lanes numbe
204 split_splittable_port(port, k, lanes, dev) global() argument
[all...]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi65 lanes {
84 lanes {
138 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
139 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
146 phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
147 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
148 <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
149 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
150 <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
159 num-lanes
[all...]
/linux/drivers/nubus/
H A Dproc.c73 int lanes = board->lanes; in nubus_proc_add_rsrc_dir() local
79 return proc_mkdir_data(name, 0555, procdir, (void *)lanes); in nubus_proc_add_rsrc_dir()
121 int lanes = (int)proc_get_parent_data(inode); in nubus_proc_rsrc_show() local
124 if (!lanes) in nubus_proc_rsrc_show()
127 ent.mask = lanes; in nubus_proc_rsrc_show()
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt104 - If lanes 0 to 3 are used:
107 - If lanes 4 or 5 are used:
148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
150 - Root port 0 uses 4 lanes, root port 1 is unused.
151 - Both root ports use 2 lanes.
157 number of lanes in the nvidia,num-lanes property. Entries are of the form
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
210 nvidia,num-lanes
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9132-db.dtsi66 * lanes not being connected. Prevent the port for being
107 /* Generic PHY, providing serdes lanes */
155 num-lanes = <2>;
157 /* Generic PHY, providing serdes lanes */
165 num-lanes = <1>;
167 /* Generic PHY, providing serdes lanes */
176 /* Generic PHY, providing serdes lanes */
224 /* Generic PHY, providing serdes lanes */
/linux/drivers/gpu/drm/rockchip/
H A Dcdn-dp-core.c157 u8 lanes; in cdn_dp_get_port_lanes() local
164 lanes = 2; in cdn_dp_get_port_lanes()
166 lanes = 4; in cdn_dp_get_port_lanes()
168 lanes = 0; in cdn_dp_get_port_lanes()
171 return lanes; in cdn_dp_get_port_lanes()
191 int i, lanes; in cdn_dp_connected_port() local
195 lanes = cdn_dp_get_port_lanes(port); in cdn_dp_connected_port()
196 if (lanes) in cdn_dp_connected_port()
269 u8 lanes, bpc; in cdn_dp_bridge_mode_valid() local
289 source_max = dp->lanes; in cdn_dp_bridge_mode_valid()
466 int ret, i, lanes; cdn_dp_enable() local
917 unsigned int lanes = dp->max_lanes; cdn_dp_pd_event_work() local
[all...]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.c68 u32 lanes[4]; member
107 dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]); in rockchip_p3phy_rk3568_init()
108 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3568_init()
165 if (priv->lanes[i] > 1) in rockchip_p3phy_rk3588_init()
167 if (priv->lanes[i] == 3) in rockchip_p3phy_rk3588_init()
169 if (priv->lanes[i] == 4) in rockchip_p3phy_rk3588_init()
284 priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes", in rockchip_p3phy_probe()
285 priv->lanes, 2, in rockchip_p3phy_probe()
286 ARRAY_SIZE(priv->lanes)); in rockchip_p3phy_probe()
288 /* if no data-lanes assum in rockchip_p3phy_probe()
[all...]
/linux/drivers/staging/media/ipu7/
H A Dipu7-isys-csi-phy.c226 u32 id, lanes, phy_mode; in ipu7_isys_csi_ctrl_cfg() local
230 lanes = csi2->nlanes; in ipu7_isys_csi_ctrl_cfg()
232 dev_dbg(dev, "csi-%d controller init with %u lanes, phy mode %u", in ipu7_isys_csi_ctrl_cfg()
233 id, lanes, phy_mode); in ipu7_isys_csi_ctrl_cfg()
238 /* num of active data lanes */ in ipu7_isys_csi_ctrl_cfg()
239 dwc_csi_write(isys, id, N_LANES, lanes - 1); in ipu7_isys_csi_ctrl_cfg()
447 static void ipu7_isys_dphy_config(struct ipu7_isys *isys, u8 id, u8 lanes, in ipu7_isys_dphy_config() argument
499 for (i = 0; i < lanes + 1; i++) in ipu7_isys_dphy_config()
505 for (i = 0; i < lanes; i++) in ipu7_isys_dphy_config()
527 if (lanes in ipu7_isys_dphy_config()
725 ipu7_isys_cphy_config(struct ipu7_isys * isys,u8 id,u8 lanes,bool aggregation,u64 mbps) ipu7_isys_cphy_config() argument
870 ipu7_isys_phy_config(struct ipu7_isys * isys,u8 id,u8 lanes,bool aggregation) ipu7_isys_phy_config() argument
956 u32 lanes = csi2->nlanes; ipu7_isys_csi_phy_powerup() local
[all...]
/linux/drivers/phy/cadence/
H A Dcdns-dphy-rx.c129 unsigned int lanes) in cdns_dphy_rx_wait_lane_ready() argument
145 for (i = 0; i < lanes; i++) { in cdns_dphy_rx_wait_lane_ready()
172 unsigned int reg, lanes = opts->mipi_dphy.lanes; in cdns_dphy_rx_configure() local
185 /* Data lanes. Minimum one lane is mandatory. */ in cdns_dphy_rx_configure()
186 if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) in cdns_dphy_rx_configure()
206 ret = cdns_dphy_rx_wait_lane_ready(dphy, lanes); in cdns_dphy_rx_configure()
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h270 * @lanes:
272 * Number of active, consecutive, data lanes, starting from
275 unsigned char lanes; member
280 unsigned int lanes,
283 unsigned int lanes,

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