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Searched refs:lane (Results 1 – 25 of 226) sorted by relevance

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/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
71 #define LYNX_28G_LNaTECR0(lane) ( argument
74 LYNX_28G_LNaRRSTCTL(lane) global() argument
81 LYNX_28G_LNaRGCR0(lane) global() argument
91 LYNX_28G_LNaRGCR1(lane) global() argument
93 LYNX_28G_LNaRECR0(lane) global() argument
94 LYNX_28G_LNaRECR1(lane) global() argument
95 LYNX_28G_LNaRECR2(lane) global() argument
97 LYNX_28G_LNaRSCCR0(lane) global() argument
99 LYNX_28G_LNaPSS(lane) global() argument
104 LYNX_28G_SGMIIaCR1(lane) global() argument
135 struct lynx_28g_lane lane[LYNX_28G_NUM_LANE]; global() member
152 lynx_28g_lane_rmw(lane,reg,val,mask) global() argument
155 lynx_28g_lane_read(lane,reg) global() argument
194 lynx_28g_lane_set_nrate(struct lynx_28g_lane * lane,struct lynx_28g_pll * pll,phy_interface_t intf) lynx_28g_lane_set_nrate() argument
227 lynx_28g_lane_set_pll(struct lynx_28g_lane * lane,struct lynx_28g_pll * pll) lynx_28g_lane_set_pll() argument
239 lynx_28g_cleanup_lane(struct lynx_28g_lane * lane) lynx_28g_cleanup_lane() argument
262 lynx_28g_lane_set_sgmii(struct lynx_28g_lane * lane) lynx_28g_lane_set_sgmii() argument
298 lynx_28g_lane_set_10gbaser(struct lynx_28g_lane * lane) lynx_28g_lane_set_10gbaser() argument
336 struct lynx_28g_lane *lane = phy_get_drvdata(phy); lynx_28g_power_off() local
360 struct lynx_28g_lane *lane = phy_get_drvdata(phy); lynx_28g_power_on() local
384 struct lynx_28g_lane *lane = phy_get_drvdata(phy); lynx_28g_set_mode() local
434 struct lynx_28g_lane *lane = phy_get_drvdata(phy); lynx_28g_validate() local
448 struct lynx_28g_lane *lane = phy_get_drvdata(phy); lynx_28g_init() local
512 struct lynx_28g_lane *lane; lynx_28g_cdr_lock_check() local
540 lynx_28g_lane_read_configuration(struct lynx_28g_lane * lane) lynx_28g_lane_read_configuration() argument
589 struct lynx_28g_lane *lane = &priv->lane[i]; lynx_28g_probe() local
[all...]
H A Dphy-fsl-imx8qm-hsio.c96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
129 lane->phy_off = 0; in imx_hsio_init()
132 if (lane->idx == 0) in imx_hsio_init()
133 lane in imx_hsio_init()
191 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_exit() local
200 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_pcie_phy_resets() local
231 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_sata_phy_resets() local
251 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_configure_clk_pad() local
273 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_pre_set() local
292 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_pcie_power_on() local
321 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_sata_power_on() local
349 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_power_on() local
390 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_power_off() local
453 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_set_mode() local
483 struct imx_hsio_lane *lane = phy_get_drvdata(phy); imx_hsio_set_speed() local
580 struct imx_hsio_lane *lane = &priv->lane[i]; imx_hsio_probe() local
[all...]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c40 * When accessing common PHY lane registers directly, we need to shift by 1,
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane
397 comphy_lane_reg_set(struct mvebu_a3700_comphy_lane * lane,u16 reg,u16 data,u16 mask) comphy_lane_reg_set() argument
415 comphy_lane_reg_poll(struct mvebu_a3700_comphy_lane * lane,u16 reg,u16 bits,ulong sleep_us,ulong timeout_us) comphy_lane_reg_poll() argument
447 comphy_periph_reg_set(struct mvebu_a3700_comphy_lane * lane,u8 reg,u32 data,u32 mask) comphy_periph_reg_set() argument
454 comphy_periph_reg_poll(struct mvebu_a3700_comphy_lane * lane,u8 reg,u32 bits,ulong sleep_us,ulong timeout_us) comphy_periph_reg_poll() argument
468 mvebu_a3700_comphy_set_phy_selector(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_set_phy_selector() argument
532 mvebu_a3700_comphy_sata_power_on(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_sata_power_on() argument
599 comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane * lane,bool is_1gbps) comphy_gbe_phy_init() argument
629 mvebu_a3700_comphy_ethernet_power_on(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_ethernet_power_on() argument
821 mvebu_a3700_comphy_usb3_power_on(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_usb3_power_on() argument
986 mvebu_a3700_comphy_pcie_power_on(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_pcie_power_on() argument
1074 mvebu_a3700_comphy_sata_power_off(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_sata_power_off() argument
1086 mvebu_a3700_comphy_ethernet_power_off(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_ethernet_power_off() argument
1097 mvebu_a3700_comphy_pcie_power_off(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_pcie_power_off() argument
1104 mvebu_a3700_comphy_usb3_power_off(struct mvebu_a3700_comphy_lane * lane) mvebu_a3700_comphy_usb3_power_off() argument
1112 mvebu_a3700_comphy_check_mode(int lane,enum phy_mode mode,int submode) mvebu_a3700_comphy_check_mode() argument
1138 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); mvebu_a3700_comphy_set_mode() local
1159 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); mvebu_a3700_comphy_power_on() local
1188 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); mvebu_a3700_comphy_power_off() local
1219 struct mvebu_a3700_comphy_lane *lane; mvebu_a3700_comphy_xlate() local
1306 struct mvebu_a3700_comphy_lane *lane; mvebu_a3700_comphy_probe() local
[all...]
H A Dphy-mvebu-cp110-comphy.c129 * A lane is described by the following bitfields:
182 unsigned lane; member
190 .lane = _lane, \
200 .lane = _lane, \
209 /* lane 0 */
214 /* lane 1 */
221 /* lane 2 */
230 /* lane 3 */
237 /* lane 4 */
250 /* lane
277 mvebu_comphy_smc(unsigned long function,unsigned long phys,unsigned long lane,unsigned long mode) mvebu_comphy_smc() argument
295 mvebu_comphy_get_mode(bool fw_mode,int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_mode() argument
325 mvebu_comphy_get_mux(int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_mux() argument
331 mvebu_comphy_get_fw_mode(int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_fw_mode() argument
337 mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane * lane) mvebu_comphy_ethernet_init_reset() argument
453 mvebu_comphy_init_plls(struct mvebu_comphy_lane * lane) mvebu_comphy_init_plls() argument
496 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode_sgmii() local
529 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode_rxaui() local
582 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode_10gbaser() local
724 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_on_legacy() local
768 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_on() local
856 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_set_mode() local
876 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_off_legacy() local
899 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); mvebu_comphy_power_off() local
922 struct mvebu_comphy_lane *lane; mvebu_comphy_xlate() local
1037 struct mvebu_comphy_lane *lane; mvebu_comphy_probe() local
[all...]
H A Dphy-armada38x-comphy.c47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 * row index = serdes lane,
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
79 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
84 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
85 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
88 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
97 a38x_comphy_poll(struct a38x_comphy_lane * lane,unsigned int offset,u32 mask,u32 value) a38x_comphy_poll() argument
120 struct a38x_comphy_lane *lane = phy_get_drvdata(phy); a38x_comphy_set_mode() local
165 struct a38x_comphy_lane *lane; a38x_comphy_xlate() local
[all...]
/linux/drivers/net/dsa/b53/
H A Db53_serdes.c42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane in b53_serdes_config() local
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; b53_serdes_an_restart() local
106 u8 lane = pcs_to_b53_pcs(pcs)->lane; b53_serdes_get_state() local
142 u8 lane = b53_serdes_map_lane(dev, port); b53_serdes_link_set() local
168 u8 lane = b53_serdes_map_lane(dev, port); b53_serdes_phylink_get_caps() local
198 u8 lane = b53_serdes_map_lane(dev, port); b53_serdes_phylink_mac_select_pcs() local
214 u8 lane = b53_serdes_map_lane(dev, port); b53_serdes_init() local
[all...]
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
80 uint8_t lane in dp_fixed_vs_pe_set_retimer_lane_settings() local
106 uint8_t lane = 0; perform_fixed_vs_pe_nontransparent_training_sequence() local
212 uint8_t lane = 0; dp_perform_fixed_vs_pe_training_sequence() local
[all...]
H A Dlink_dp_training.c305 uint32_t lane; in maximize_lane_settings() local
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) in maximize_lane_settings()
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; in maximize_lane_settings()
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS) in maximize_lane_settings()
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS; in maximize_lane_settings()
319 if (lane_settings[lane].FFE_PRESET.settings.level > in maximize_lane_settings()
322 lane_settings[lane] in maximize_lane_settings()
359 uint8_t lane = 0; dp_hw_to_dpcd_lane_settings() local
465 uint32_t lane; dp_is_max_vs_reached() local
481 uint32_t lane; dp_is_cr_done() local
495 uint32_t lane; dp_is_ch_eq_done() local
506 uint32_t lane; dp_is_symbol_locked() local
561 uint32_t lane; dp_check_link_loss_status() local
606 uint32_t lane; dp_get_lane_status_and_lane_adjust() local
683 uint32_t lane; override_lane_settings() local
724 uint32_t lane; override_training_settings() local
859 uint32_t lane; dp_decide_lane_settings() local
1426 uint32_t lane; perform_post_lt_adj_req_sequence() local
[all...]
/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
156 #define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) argument
163 #define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) argument
170 #define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) argument
177 #define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), argument
181 VLV_TX_DW11(ch,lane) global() argument
184 VLV_TX_DW14(ch,lane) global() argument
290 CHV_TX_DW0(ch,lane) global() argument
291 CHV_TX_DW1(ch,lane) global() argument
292 CHV_TX_DW2(ch,lane) global() argument
293 CHV_TX_DW3(ch,lane) global() argument
294 CHV_TX_DW4(ch,lane) global() argument
295 CHV_TX_DW5(ch,lane) global() argument
296 CHV_TX_DW6(ch,lane) global() argument
297 CHV_TX_DW7(ch,lane) global() argument
298 CHV_TX_DW8(ch,lane) global() argument
299 CHV_TX_DW9(ch,lane) global() argument
300 CHV_TX_DW10(ch,lane) global() argument
302 CHV_TX_DW11(ch,lane) global() argument
306 CHV_TX_DW14(ch,lane) global() argument
[all...]
H A Dintel_cx0_phy_regs.h39 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
43 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
44 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ argument
46 _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
47 _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
59 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
63 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
64 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ argument
66 _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
67 _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
125 XELPDP_LANE_PIPE_RESET(lane) global() argument
126 XELPDP_LANE_PHY_CURRENT_STATUS(lane) global() argument
127 XELPDP_LANE_POWERDOWN_UPDATE(lane) global() argument
132 XELPDP_LANE_POWERDOWN_NEW_STATE(lane,val) global() argument
162 _XELPDP_PORT_MSGBUS_TIMER(port,lane) global() argument
167 XELPDP_PORT_MSGBUS_TIMER(i915__,port,lane) global() argument
188 XELPDP_LANE_PCLK_PLL_REQUEST(lane) global() argument
189 XELPDP_LANE_PCLK_PLL_ACK(lane) global() argument
190 XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) global() argument
191 XELPDP_LANE_PCLK_REFCLK_ACK(lane) global() argument
280 PHY_CX0_VDROVRD_CTL(lane,tx,control) global() argument
[all...]
H A Dbxt_dpio_phy_regs.h28 #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ argument
29 ((lane) & 1) * 0x80)
30 #define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \ argument
31 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
101 /* BXT PHY common lane registers */
209 #define BXT_PORT_TX_DW2_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
226 #define BXT_PORT_TX_DW3_LN(phy, ch, lane) _MMIO_BXT_PHY_CH_LN(phy, ch, lane, \ argument
241 BXT_PORT_TX_DW4_LN(phy,ch,lane) global() argument
256 BXT_PORT_TX_DW5_LN(phy,ch,lane) global() argument
269 BXT_PORT_TX_DW14_LN(phy,ch,lane) global() argument
[all...]
H A Dintel_cx0_phy.c74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
93 int lane; in intel_cx0_program_msgbus_timer() local
95 for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane) in intel_cx0_program_msgbus_timer()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
134 int lane) in intel_clear_response_ready_flag() argument
139 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
143 static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane) in intel_cx0_bus_reset() argument
149 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in intel_cx0_bus_reset()
152 if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), in intel_cx0_bus_reset()
165 intel_cx0_wait_for_ack(struct intel_encoder * encoder,int command,int lane,u32 * val) intel_cx0_wait_for_ack() argument
213 __intel_cx0_read_once(struct intel_encoder * encoder,int lane,u16 addr) __intel_cx0_read_once() argument
253 __intel_cx0_read(struct intel_encoder * encoder,int lane,u16 addr) __intel_cx0_read() argument
279 int lane = lane_mask_to_lane(lane_mask); intel_cx0_read() local
285 __intel_cx0_write_once(struct intel_encoder * encoder,int lane,u16 addr,u8 data,bool committed) __intel_cx0_write_once() argument
344 __intel_cx0_write(struct intel_encoder * encoder,int lane,u16 addr,u8 data,bool committed) __intel_cx0_write() argument
367 int lane; intel_cx0_write() local
374 intel_c20_sram_write(struct intel_encoder * encoder,int lane,u16 addr,u16 data) intel_c20_sram_write() argument
388 intel_c20_sram_read(struct intel_encoder * encoder,int lane,u16 addr) intel_c20_sram_read() argument
406 __intel_cx0_rmw(struct intel_encoder * encoder,int lane,u16 addr,u8 clear,u8 set,bool committed) __intel_cx0_rmw() argument
420 u8 lane; intel_cx0_rmw() local
492 int lane = ln / 2; intel_cx0_phy_set_signal_levels() local
2111 u8 lane = INTEL_CX0_LANE0; intel_c10pll_readout_hw_state() local
2792 int lane = 0; intel_cx0_get_powerdown_update() local
2803 int lane = 0; intel_cx0_get_powerdown_state() local
2818 int lane; intel_cx0_powerdown_change_sequence() local
2866 int lane = 0; intel_cx0_get_pclk_refclk_request() local
2877 int lane = 0; intel_cx0_get_pclk_refclk_ack() local
2992 int lane = 0; intel_cx0_get_pclk_pll_request() local
3003 int lane = 0; intel_cx0_get_pclk_pll_ack() local
3342 u8 lane = dig_port->lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; intel_cx0_pll_is_enabled() local
[all...]
/linux/drivers/phy/tegra/
H A Dxusb.c115 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
118 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
126 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
128 dev_err(dev, "invalid function \"%s\" for lane \"%pOFn\"\n", in tegra_xusb_lane_parse_dt()
133 lane->function = err; in tegra_xusb_lane_parse_dt()
141 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
191 struct phy *lane; in tegra_xusb_pad_register() local
208 struct tegra_xusb_lane *lane; tegra_xusb_pad_register() local
320 tegra_xusb_lane_program(struct tegra_xusb_lane * lane) tegra_xusb_lane_program() argument
348 struct tegra_xusb_lane *lane; tegra_xusb_pad_program() local
391 tegra_xusb_lane_check(struct tegra_xusb_lane * lane,const char * function) tegra_xusb_lane_check() argument
403 struct tegra_xusb_lane *lane, *hit = ERR_PTR(-ENODEV); tegra_xusb_find_lane() local
426 struct tegra_xusb_lane *lane, *match = ERR_PTR(-ENODEV); tegra_xusb_port_find_lane() local
662 struct tegra_xusb_lane *lane; tegra_xusb_setup_usb_role_switch() local
1397 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_enable_phy_sleepwalk() local
1408 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_disable_phy_sleepwalk() local
1419 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_enable_phy_wake() local
1430 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_disable_phy_wake() local
1441 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_xusb_padctl_remote_wake_detected() local
1473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra_phy_xusb_utmi_port_reset() local
1485 struct tegra_xusb_lane *lane; tegra_phy_xusb_utmi_pad_power_on() local
1501 struct tegra_xusb_lane *lane; tegra_phy_xusb_utmi_pad_power_down() local
1538 struct tegra_xusb_lane *lane; tegra_xusb_padctl_get_port_number() local
[all...]
H A Dxusb.h55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
107 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
125 to_sata_lane(struct tegra_xusb_lane * lane) to_sata_lane() argument
279 struct tegra_xusb_lane *lane; global() member
[all...]
H A Dxusb-tegra210.c447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb in tegra210_sata_uphy_enable()
1058 tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane * lane,enum usb_device_speed speed) tegra210_usb3_enable_phy_sleepwalk() argument
1090 tegra210_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane * lane) tegra210_usb3_disable_phy_sleepwalk() argument
1119 tegra210_usb3_enable_phy_wake(struct tegra_xusb_lane * lane) tegra210_usb3_enable_phy_wake() argument
1150 tegra210_usb3_disable_phy_wake(struct tegra_xusb_lane * lane) tegra210_usb3_disable_phy_wake() argument
1181 tegra210_usb3_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra210_usb3_phy_remote_wake_detected() argument
1197 tegra210_utmi_enable_phy_wake(struct tegra_xusb_lane * lane) tegra210_utmi_enable_phy_wake() argument
1222 tegra210_utmi_disable_phy_wake(struct tegra_xusb_lane * lane) tegra210_utmi_disable_phy_wake() argument
1247 tegra210_utmi_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra210_utmi_phy_remote_wake_detected() argument
1261 tegra210_hsic_enable_phy_wake(struct tegra_xusb_lane * lane) tegra210_hsic_enable_phy_wake() argument
1286 tegra210_hsic_disable_phy_wake(struct tegra_xusb_lane * lane) tegra210_hsic_disable_phy_wake() argument
1311 tegra210_hsic_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra210_hsic_phy_remote_wake_detected() argument
1335 tegra210_pmc_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane * lane,enum usb_device_speed speed) tegra210_pmc_utmi_enable_phy_sleepwalk() argument
1508 tegra210_pmc_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane * lane) tegra210_pmc_utmi_disable_phy_sleepwalk() argument
1556 tegra210_pmc_hsic_enable_phy_sleepwalk(struct tegra_xusb_lane * lane,enum usb_device_speed speed) tegra210_pmc_hsic_enable_phy_sleepwalk() argument
1658 tegra210_pmc_hsic_disable_phy_sleepwalk(struct tegra_xusb_lane * lane) tegra210_pmc_hsic_disable_phy_sleepwalk() argument
1699 struct tegra_xusb_lane *lane; tegra210_usb3_set_lfps_detect() local
1781 tegra210_usb2_lane_remove(struct tegra_xusb_lane * lane) tegra210_usb2_lane_remove() argument
1800 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb2_phy_init() local
1835 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb2_phy_exit() local
1916 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb2_phy_set_mode() local
1954 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb2_phy_power_on() local
2114 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb2_phy_power_off() local
2277 tegra210_hsic_lane_remove(struct tegra_xusb_lane * lane) tegra210_hsic_lane_remove() argument
2296 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_hsic_phy_init() local
2317 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_hsic_phy_power_on() local
2402 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_hsic_phy_power_off() local
2496 tegra210_uphy_lane_iddq_enable(struct tegra_xusb_lane * lane) tegra210_uphy_lane_iddq_enable() argument
2515 tegra210_uphy_lane_iddq_disable(struct tegra_xusb_lane * lane) tegra210_uphy_lane_iddq_disable() argument
2563 tegra210_lane_to_usb3_port(struct tegra_xusb_lane * lane) tegra210_lane_to_usb3_port() argument
2580 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb3_phy_power_on() local
2653 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_usb3_phy_power_off() local
2710 tegra210_pcie_lane_remove(struct tegra_xusb_lane * lane) tegra210_pcie_lane_remove() argument
2731 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_pcie_phy_init() local
2745 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_pcie_phy_power_on() local
2760 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_pcie_phy_power_off() local
2880 tegra210_sata_lane_remove(struct tegra_xusb_lane * lane) tegra210_sata_lane_remove() argument
2901 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_sata_phy_init() local
2914 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_sata_phy_power_on() local
2929 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra210_sata_phy_power_off() local
3089 struct tegra_xusb_lane *lane; tegra210_utmi_port_reset() local
3204 struct tegra_xusb_lane *lane; tegra210_xusb_padctl_restore() local
[all...]
H A Dxusb-tegra124.c292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane in tegra124_usb2_phy_exit() local
480 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_usb2_phy_power_on() local
569 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_usb2_phy_power_off() local
701 tegra124_ulpi_lane_remove(struct tegra_xusb_lane * lane) tegra124_ulpi_lane_remove() argument
715 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_ulpi_phy_init() local
722 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_ulpi_phy_exit() local
837 tegra124_hsic_lane_remove(struct tegra_xusb_lane * lane) tegra124_hsic_lane_remove() argument
851 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_hsic_phy_init() local
858 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_hsic_phy_exit() local
865 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_hsic_phy_power_on() local
935 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_hsic_phy_power_off() local
1057 tegra124_pcie_lane_remove(struct tegra_xusb_lane * lane) tegra124_pcie_lane_remove() argument
1071 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_pcie_phy_init() local
1078 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_pcie_phy_exit() local
1085 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_pcie_phy_power_on() local
1126 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_pcie_phy_power_off() local
1235 tegra124_sata_lane_remove(struct tegra_xusb_lane * lane) tegra124_sata_lane_remove() argument
1249 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_sata_phy_init() local
1256 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_sata_phy_exit() local
1263 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_sata_phy_power_on() local
1308 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra124_sata_phy_power_off() local
1480 struct tegra_xusb_lane *lane = usb3->base.lane; tegra124_usb3_port_enable() local
[all...]
H A Dxusb-tegra186.c323 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra186_usb2_lane_remove() argument
325 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove()
330 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra186_utmi_enable_phy_sleepwalk() argument
333 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_enable_phy_sleepwalk()
335 unsigned int index = lane->index; in tegra186_utmi_enable_phy_sleepwalk()
479 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane) in tegra186_utmi_disable_phy_sleepwalk() argument
481 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_disable_phy_sleepwalk()
483 unsigned int index = lane->index; in tegra186_utmi_disable_phy_sleepwalk()
527 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane) in tegra186_utmi_enable_phy_wake() argument
529 struct tegra_xusb_padctl *padctl = lane in tegra186_utmi_enable_phy_wake()
552 tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane * lane) tegra186_utmi_disable_phy_wake() argument
577 tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra186_utmi_phy_remote_wake_detected() argument
685 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_pad_power_on() local
729 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_pad_power_down() local
840 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_set_mode() local
871 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_power_on() local
949 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_init() local
987 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_utmi_phy_exit() local
1132 tegra186_usb3_lane_remove(struct tegra_xusb_lane * lane) tegra186_usb3_lane_remove() argument
1139 tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane * lane,enum usb_device_speed speed) tegra186_usb3_enable_phy_sleepwalk() argument
1165 tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane * lane) tegra186_usb3_disable_phy_sleepwalk() argument
1188 tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane * lane) tegra186_usb3_enable_phy_wake() argument
1213 tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane * lane) tegra186_usb3_disable_phy_wake() argument
1238 tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane * lane) tegra186_usb3_phy_remote_wake_detected() argument
1285 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_usb3_phy_power_on() local
1354 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); tegra186_usb3_phy_power_off() local
[all...]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dserdes.c37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
39 return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); in mv88e6390_serdes_read()
243 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
250 lane = MV88E6341_PORT5_LANE; in mv88e6341_serdes_get_lane()
254 return lane; in mv88e6341_serdes_get_lane()
260 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
267 lane = MV88E6390_PORT9_LANE0; in mv88e6390_serdes_get_lane()
273 lane = MV88E6390_PORT10_LANE0; in mv88e6390_serdes_get_lane()
277 return lane; in mv88e6390_serdes_get_lane()
285 int lane in mv88e6390x_serdes_get_lane() local
361 int lane = -ENODEV; mv88e6393x_serdes_get_lane() local
412 mv88e6390_serdes_get_stat(struct mv88e6xxx_chip * chip,int lane,struct mv88e6390_serdes_hw_stat * stat) mv88e6390_serdes_get_stat() argument
434 int lane; mv88e6390_serdes_get_stats() local
493 int lane; mv88e6390_serdes_get_regs() local
[all...]
/linux/drivers/phy/
H A Dphy-xgene.c268 /* PHY lane CSR accessing from SDS indirectly */
520 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u3 argument
944 int lane; xgene_phy_sata_cfg_lanes() local
1344 xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx * ctx,int lane) xgene_phy_force_lat_summer_cal() argument
1410 xgene_phy_reset_rxd(struct xgene_phy_ctx * ctx,int lane) xgene_phy_reset_rxd() argument
1424 xgene_phy_gen_avg_val(struct xgene_phy_ctx * ctx,int lane) xgene_phy_gen_avg_val() argument
[all...]
/linux/sound/soc/tegra/
H A Dtegra186_asrc.c108 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
115 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
120 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
172 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
195 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
205 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
224 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
226 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
229 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
232 asrc->lane[i in tegra186_asrc_out_hw_params()
[all...]
/linux/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c21 unsigned int lane; member
53 if (p_rt->lane != t_data->lane) in sdw_compute_slave_ports()
64 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_slave_ports()
156 if (p_rt->lane != params->lane) in sdw_compute_master_ports()
162 SDW_BLK_PKG_PER_PORT, p_rt->lane); in sdw_compute_master_ports()
184 t_data.lane = params->lane; in sdw_compute_master_ports()
199 /* reset hstop for each lane */ in _sdw_compute_port_params()
294 sdw_add_element_group_count(struct sdw_group * group,unsigned int rate,unsigned int lane) sdw_add_element_group_count() argument
468 is_lane_connected_to_all_peripherals(struct sdw_master_runtime * m_rt,unsigned int lane) is_lane_connected_to_all_peripherals() argument
[all...]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-typec.c505 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
507 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
508 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
509 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
510 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
511 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
512 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
515 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
517 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
518 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
529 tcphy_dp_cfg_lane(struct rockchip_typec_phy * tcphy,u32 lane) tcphy_dp_cfg_lane() argument
[all...]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c230 int lane, lane_count, retval; in analogix_dp_link_start() local
237 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
238 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
269 dp->link_train.training_lane[lane] = in analogix_dp_link_start()
284 for (lane in analogix_dp_link_start()
296 analogix_dp_get_lane_status(u8 link_status[2],int lane) analogix_dp_get_lane_status() argument
306 int lane; analogix_dp_clock_recovery_ok() local
320 int lane; analogix_dp_channel_eq_ok() local
337 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],int lane) analogix_dp_get_adjust_request_voltage() argument
347 analogix_dp_get_adjust_request_pre_emphasis(u8 adjust_request[2],int lane) analogix_dp_get_adjust_request_pre_emphasis() argument
366 int lane, lane_count; analogix_dp_get_adjust_training_lane() local
389 int lane, lane_count, retval; analogix_dp_process_clock_recovery() local
[all...]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
51 * @num_lanes: supported lane numbers
67 * @efuse: pointer to eFuse data for each lane
81 unsigned int lane) in mtk_pcie_efuse_set_lane() argument
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
90 lane * PEXTP_ANA_LANE_OFFSET; in mtk_pcie_efuse_set_lane()
134 unsigned int lane) in mtk_pcie_efuse_read_for_lane() argument
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane()
141 snprintf(efuse_id, sizeof(efuse_id), "tx_ln%d_pmos", lane); in mtk_pcie_efuse_read_for_lane()
[all...]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-errata.c51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
54 for (lane = 0; lane < 4; lane++) { in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()
56 * Each lane has 268 bits. We need to set in __cvmx_helper_errata_qlm_disable_2nd_order_cdr()

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