| /linux/drivers/hwmon/ |
| H A D | lm75.c | 64 * @clr_mask: Bits to clear in configuration register when configuring
88 u16 clr_mask; member
132 .clr_mask = 1 << 5, /* not one-shot mode */
154 .clr_mask = 3 << 5,
163 .clr_mask = 3 << 5,
172 .clr_mask = 3 << 5,
226 .clr_mask = 1 << 1 | 1 << 7, /* disable SMBAlert and one-shot */
243 .clr_mask = 1 << 7, /* not one-shot mode */
253 .clr_mask = 1 << 7, /* not one-shot mode */
262 .clr_mask
344 lm75_write_config(struct lm75_data * data,u16 set_mask,u16 clr_mask) lm75_write_config() argument
[all...] |
| H A D | max31730.c | 61 u8 clr_mask) in max31730_write_config() argument
65 clr_mask |= MAX31730_EXTRANGE; in max31730_write_config()
66 value = data->current_conf & ~clr_mask; in max31730_write_config()
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| /linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_eq.c | 397 if (dev->eq_table.clr_mask) in mthca_tavor_interrupt()
398 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_tavor_interrupt()
437 if (dev->eq_table.clr_mask) in mthca_arbel_interrupt()
438 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_arbel_interrupt()
786 dev->eq_table.clr_mask = 0; in mthca_init_eq_table()
788 dev->eq_table.clr_mask = in mthca_init_eq_table()
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| H A D | mthca_dev.h | 228 u32 clr_mask; member
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| /linux/drivers/net/phy/ |
| H A D | bcm7xxx.c | 224 int set_mask, int clr_mask) in __phy_set_clr_bits() argument
232 v &= ~clr_mask; in __phy_set_clr_bits()
243 int set_mask, int clr_mask) in phy_set_clr_bits() argument
248 ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask); in phy_set_clr_bits()
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| /linux/drivers/mfd/ |
| H A D | ssbi.c | 93 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) in ssbi_wait_mask() argument
100 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) in ssbi_wait_mask()
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| /linux/drivers/gpio/ |
| H A D | gpio-rtd.c | 430 u32 clr_mask = BIT(hwirq % 31) << 1; in rtd_gpio_enable_irq() local
446 writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset); in rtd_gpio_enable_irq()
447 writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset); in rtd_gpio_enable_irq()
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| /linux/drivers/media/i2c/ |
| H A D | ths8200.c | 98 uint8_t clr_mask, uint8_t val_mask) in ths8200_write_and_or() argument
100 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); in ths8200_write_and_or()
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| H A D | adv7511-v4l2.c | 209 static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask) in adv7511_wr_and_or() argument
211 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask); in adv7511_wr_and_or()
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| /linux/drivers/dma/qcom/ |
| H A D | bam_dma.c | 905 u32 clr_mask = 0, srcs = 0; in bam_dma_irq() local
919 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); in bam_dma_irq()
927 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); in bam_dma_irq()
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| /linux/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | eq.c | 856 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); in mlx4_interrupt()
1205 priv->eq_table.clr_mask = in mlx4_init_eq_table()
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| H A D | mlx4.h | 695 u32 clr_mask; member
|