| /linux/drivers/mailbox/ |
| H A D | hi6220-mailbox.c | 62 unsigned int dir, dst_irq, ack_irq; member
187 writel(BIT(mchan->ack_irq), ACK_INT_CLR_REG(mbox->ipc)); in hi6220_mbox_interrupt()
202 writel(BIT(mchan->ack_irq), ACK_INT_ENA_REG(mbox->ipc)); in hi6220_mbox_startup()
212 writel(BIT(mchan->ack_irq), ACK_INT_DIS_REG(mbox->ipc)); in hi6220_mbox_shutdown()
213 mbox->irq_map_chan[mchan->ack_irq] = NULL; in hi6220_mbox_shutdown()
231 unsigned int ack_irq = spec->args[2]; in hi6220_mbox_xlate() local
235 ack_irq >= mbox->chan_num) { in hi6220_mbox_xlate()
237 "Invalid channel idx %d dst_irq %d ack_irq %d\n", in hi6220_mbox_xlate()
238 i, dst_irq, ack_irq); in hi6220_mbox_xlate()
244 if (mbox->irq_map_chan[ack_irq] in hi6220_mbox_xlate()
[all...] |
| H A D | hi3660-mailbox.c | 50 * @ack_irq: Interrupt vector for local processor
58 unsigned int ack_irq; member
107 writel(BIT(mchan->ack_irq), base + MBOX_ICLR_REG); in hi3660_mbox_check_state()
144 writel(BIT(mchan->ack_irq), base + MBOX_SRC_REG); in hi3660_mbox_acquire_channel()
148 if (val & BIT(mchan->ack_irq)) in hi3660_mbox_acquire_channel()
202 writel(BIT(mchan->ack_irq), base + MBOX_SEND_REG); in hi3660_mbox_send_data()
225 mchan->ack_irq = spec->args[2]; in hi3660_mbox_xlate()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mxgpu_ai.c | 381 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
382 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
395 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
411 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
425 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
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| H A D | mxgpu_vi.c | 580 adev->virt.ack_irq.num_types = 1; in xgpu_vi_mailbox_set_irq_funcs()
581 adev->virt.ack_irq.funcs = &xgpu_vi_mailbox_ack_irq_funcs; in xgpu_vi_mailbox_set_irq_funcs()
594 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq); in xgpu_vi_mailbox_add_irq_id()
610 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_vi_mailbox_get_irq()
623 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_vi_mailbox_put_irq()
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| H A D | mxgpu_nv.c | 451 adev->virt.ack_irq.num_types = 1; in xgpu_nv_mailbox_set_irq_funcs()
452 adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs; in xgpu_nv_mailbox_set_irq_funcs()
465 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_nv_mailbox_add_irq_id()
481 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_get_irq()
495 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_put_irq()
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| H A D | amdgpu_virt.h | 266 struct amdgpu_irq_src ack_irq; member
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| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | hisilicon,hi3660-mailbox.txt | 15 <&phandle channel dst_irq ack_irq>
19 ack_irq : Local interrupt vector
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| H A D | hisilicon,hi6220-mailbox.txt | 21 <&phandle slot_id dst_irq ack_irq>
25 ack_irq: IRQ identifier index number with generating a
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| /linux/drivers/misc/ocxl/ |
| H A D | link.c | 118 static void ack_irq(struct spa *spa, enum xsl_response r) in ack_irq() function
186 ack_irq(spa, r); in xsl_fault_handler_bh()
214 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
233 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
244 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
261 ack_irq(spa, ADDRESS_ERROR); in xsl_fault_handler()
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| /linux/drivers/media/pci/cx18/ |
| H A D | cx18-mailbox.c | 386 u32 ack_irq, req; in mb_ack_irq() local
390 ack_irq = IRQ_EPU_TO_APU_ACK; in mb_ack_irq()
394 ack_irq = IRQ_EPU_TO_CPU_ACK; in mb_ack_irq()
413 cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); in mb_ack_irq()
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| /linux/arch/alpha/include/asm/ |
| H A D | machvec.h | 76 void (*ack_irq)(unsigned long); member
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