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Searched refs:WREG32_P (Results 1 – 25 of 69) sorted by relevance

123

/linux/drivers/gpu/drm/radeon/
H A Duvd_v1_0.c227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init()
277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start()
280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start()
281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start()
291 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); in uvd_v1_0_start()
321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start()
323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start()
342 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
344 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
355 WREG32_P(UVD_MASTINT_E in uvd_v1_0_start()
[all...]
H A Drs780_dpm.c202 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, in rs780_preset_ranges_slow_clk_fbdiv_en()
205 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, in rs780_preset_ranges_slow_clk_fbdiv_en()
214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
220 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); in rs780_preset_starting_fbdiv()
260 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
264 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
268 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, in rs780_voltage_scaling_init()
272 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init()
274 WREG32_P(FVTHROT_PWM_CTRL_REG in rs780_voltage_scaling_init()
[all...]
H A Dr600_dpm.c245 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
267 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable()
269 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable()
275 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection()
277 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection()
282 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in r600_enable_acpi_pm()
288 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2()
290 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2()
304 WREG32_P(SCLK_PWRMGT_CNT in r600_enable_sclk_control()
[all...]
H A Dvce_v1_0.c222 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume()
223 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v1_0_resume()
224 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume()
227 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume()
230 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume()
252 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume()
295 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start()
311 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start()
313 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start()
321 WREG32_P(VCE_SOFT_RESE in vce_v1_0_start()
[all...]
H A Dvce_v2_0.c163 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume()
164 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume()
165 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
169 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume()
191 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume()
193 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()
H A Dr600_hdmi.c187 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr()
193 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr()
196 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr()
200 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr()
203 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr()
207 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr()
210 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr()
335 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_set_audio_packet()
349 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_audio_packet()
362 WREG32_P(HDMI0_60958_ in r600_set_audio_packet()
[all...]
H A Ddce3_1_afmt.c181 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr()
184 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr()
188 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr()
191 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr()
195 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr()
198 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
H A Drv6xx_dpm.c317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s()
324 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_v()
332 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
335 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
342 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s()
348 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); in rv6xx_set_memory_spread_spectrum_clk_v()
355 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
357 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
364 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
366 WREG32_P(GENERAL_PWRMG in rv6xx_enable_dynamic_spread_spectrum()
[all...]
H A Drv770_dpm.c135 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
137 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
138 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
139 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
178 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_restore_cgcg()
183 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm()
185 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm()
187 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv770_start_dpm()
199 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv770_stop_dpm()
201 WREG32_P(SCLK_PWRMGT_CNT in rv770_stop_dpm()
[all...]
H A Dcypress_dpm.c91 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
93 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
102 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
103 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
104 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
109 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
140 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); in cypress_gfx_clock_gating_enable()
142 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
144 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
145 WREG32_P(SCLK_PWRMGT_CNT in cypress_gfx_clock_gating_enable()
[all...]
H A Drv770_smc.c382 WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); in rv770_start_smc()
387 WREG32_P(SMC_IO, 0, ~SMC_RST_N); in rv770_reset_smc()
392 WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); in rv770_stop_smc_clock()
397 WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); in rv770_start_smc_clock()
421 WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); in rv770_send_msg_to_smc()
H A Dci_smc.c42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_set_smc_sram_address()
230 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
240 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
H A Dradeon_legacy_crtc.c331 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
333 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
335 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
347 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
349 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
351 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
937 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
958 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
H A Dsi_smc.c42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address()
266 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode()
276 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode()
H A Drv730_dpm.c450 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv730_start_dpm()
452 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv730_start_dpm()
454 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv730_start_dpm()
466 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv730_stop_dpm()
468 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv730_stop_dpm()
470 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in rv730_stop_dpm()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c293 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
299 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start()
306 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
335 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
337 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
339 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
341 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
358 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
361 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
372 WREG32_P(mmUVD_MASTINT_E in uvd_v4_2_start()
[all...]
H A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
337 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v3_1_start()
344 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start()
372 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start()
374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start()
376 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start()
378 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start()
398 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
409 WREG32_P(mmUVD_MASTINT_E in uvd_v3_1_start()
[all...]
H A Duvd_v5_0.c328 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
337 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
340 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
352 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v5_0_start()
382 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
401 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
404 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
414 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
417 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
448 WREG32_P(mmUVD_RBC_RB_CNT in uvd_v5_0_start()
[all...]
H A Djpeg_v3_0.c307 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v3_0_disable_static_power_gating()
311 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), 0, in jpeg_v3_0_disable_static_power_gating()
320 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), in jpeg_v3_0_enable_static_power_gating()
374 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0, in jpeg_v3_0_start()
378 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN), in jpeg_v3_0_start()
409 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), in jpeg_v3_0_stop()
H A Dsi.c1659 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1664 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1676 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in si_uvd_send_upll_ctlreq()
1796 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
1801 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
1815 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_uvd_clocks()
1818 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in si_set_uvd_clocks()
1821 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
1824 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
1833 WREG32_P(CG_UPLL_FUNC_CNT in si_set_uvd_clocks()
[all...]
H A Dvcn_v5_0_0.c718 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1, in vcn_v5_0_0_start_dpg_mode()
841 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v5_0_0_start()
845 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v5_0_0_start()
849 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0, in vcn_v5_0_0_start()
872 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0, in vcn_v5_0_0_start()
876 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v5_0_0_start()
904 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v5_0_0_start()
908 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v5_0_0_start()
922 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v5_0_0_start()
927 WREG32_P(SOC15_REG_OFFSE in vcn_v5_0_0_start()
[all...]
H A Dvcn_v5_0_1.c614 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, in vcn_v5_0_1_start_dpg_mode()
927 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), in vcn_v5_0_1_start()
931 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, in vcn_v5_0_1_start()
935 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, in vcn_v5_0_1_start()
958 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, in vcn_v5_0_1_start()
962 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, in vcn_v5_0_1_start()
990 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), in vcn_v5_0_1_start()
994 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, in vcn_v5_0_1_start()
1008 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), in vcn_v5_0_1_start()
1013 WREG32_P(SOC15_REG_OFFSE in vcn_v5_0_1_start()
[all...]
H A Dvce_v3_0.c306 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); in vce_v3_0_start()
343 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001); in vce_v3_0_stop()
553 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v3_0_mc_resume()
554 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v3_0_mc_resume()
555 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v3_0_mc_resume()
559 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v3_0_mc_resume()
596 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v3_0_mc_resume()
736 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); in vce_v3_0_set_interrupt_state()
H A Dvcn_v2_5.c1040 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
1142 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1171 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1202 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
1216 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1220 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1267 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1271 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v2_5_start()
1274 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1294 WREG32_P(SOC15_REG_OFFSE in vcn_v2_5_start()
[all...]
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_smc.c48 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); in si_set_smc_sram_address()
235 WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); in amdgpu_si_load_smc_ucode()
245 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); in amdgpu_si_load_smc_ucode()

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