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Searched refs:S5P_CLKDIV_FSYS0 (Results 1 – 3 of 3) sorted by relevance

/linux-3.3/arch/arm/mach-exynos/
Dclock-exynos4210.c67 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
Dclock.c56 SAVE_ITEM(S5P_CLKDIV_FSYS0),
/linux-3.3/arch/arm/mach-exynos/include/mach/
Dregs-clock.h67 #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) macro