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Searched refs:MI_INVALIDATE_TLB (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c221 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB); in gen6_emit_flush_xcs()
226 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD); in gen6_emit_flush_vcs()
400 *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB | in gen7_emit_breadcrumb_xcs()
H A Dgen8_engine_cs.c98 cmd |= MI_INVALIDATE_TLB; in gen8_emit_flush_xcs()
392 cmd |= MI_INVALIDATE_TLB; in gen12_emit_flush_xcs()
H A Dintel_gpu_commands.h167 #define MI_INVALIDATE_TLB (1<<18) macro
/linux/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c115 dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | MI_FLUSH_DW_OP_STOREDW | in emit_flush_invalidate()
259 seqno, MI_INVALIDATE_TLB, dw, i); in __emit_job_gen12_simple()
321 seqno, MI_INVALIDATE_TLB, dw, i); in __emit_job_gen12_video()
418 dw[i++] = MI_FLUSH_DW | MI_INVALIDATE_TLB | job->migrate_flush_flags | in emit_migration_job_gen12()
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_mi_commands.h58 #define MI_INVALIDATE_TLB REG_BIT(18) macro