Searched refs:L3C (Results 1 – 5 of 5) sorted by relevance
6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 816 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,26 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU31 e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in61 1. L3C PMU supports filtering by core/thread within the cluster which can be81 - 5'b00001: comes from L3C in this die;82 - 5'b01000: comes from L3C in the cross-die;83 - 5'b01001: comes from L3C which is in another socket;
6 L3C - L3 cache controller22 Required properties for L3C subnode:24 - reg : First resource shall be the L3C PMU resource.
177 Note: on some machines (e.g. L3C), after the module has been loaded, only 0x6n
208 The SoC has PMU support in its L3 cache controller (L3C) and