| /linux/Documentation/admin-guide/media/ |
| H A D | mgb4.rst | 119 The type of HSYNC pulses as detected by the video format detector.
130 HSYNC pulses, these must be generated internally in the FPGA to achieve
137 HSYNC pulses, these must be generated internally in the FPGA to achieve
140 internal HSYNC pulse. The value must be greater than 1 and smaller than
153 Width of the HSYNC signal in PCLK clock ticks.
165 Number of PCLK pulses between deassertion of the HSYNC signal and the first
173 line (marked by DE=1) and assertion of the HSYNC signal.
250 HSYNC signal polarity.
278 Width of the HSYNC signal in pixels. The default value is 40.
284 Number of PCLK pulses between deassertion of the HSYNC signa
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| /linux/drivers/gpu/drm/nouveau/dispnv50/ |
| H A D | dac507d.c | 37 sync |= NVVAL(NV507D, DAC_SET_POLARITY, HSYNC, asyh->or.nhsync); in dac507d_ctrl()
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r9a07g043u11-smarc-du-adv7513.dtso | 48 pinmux = <RZG2L_PORT_PINMUX(11, 0, 6)>, /* HSYNC */
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| /linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | ti,tvp514x.txt | 17 - hsync-active: HSYNC Polarity configuration for endpoint.
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| H A D | ti,tvp7002.txt | 10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
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| H A D | ovti,ov7670.txt | 13 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
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| H A D | ti,tvp5150.txt | 44 - hsync-active: Active state of the HSYNC signal. Must be <1> (HIGH).
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| /linux/drivers/video/fbdev/i810/ |
| H A D | i810_regs.h | 150 #define HSYNC 0x60008 macro
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| /linux/drivers/gpu/drm/imx/dc/ |
| H A D | dc-fg.c | 35 #define HSYNC(x) FIELD_PREP(GENMASK(13, 0), ((x) - 1)) macro
160 regmap_write(fg->reg, HTCFG2, HSYNC(hsync) | HSBP(hsbp) | HSEN); in dc_fg_cfg_videomode()
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| /linux/Documentation/fb/ |
| H A D | pxafb.rst | 39 hsynclen:HSYNC == LCCR1_HSW + 1
65 hsync:HSYNC, vsync:VSYNC
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| H A D | matroxfb.rst | 271 left:X left boundary: pixels between end of HSYNC pulse and first pixel.
273 right:X right boundary: pixels between end of picture and start of HSYNC
275 hslen:X length of HSYNC pulse, in pixels. Default is derived from `vesa`
279 sync:X sync. pulse - bit 0 inverts HSYNC polarity, bit 1 VSYNC polarity.
280 If bit 3 (value 0x08) is set, composite sync instead of HSYNC is
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| /linux/include/video/ |
| H A D | sstfb.h | 161 #define HSYNC 0x0220 macro
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6ul-tx6ul-mainboard.dts | 169 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
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| H A D | imx6qdl-kontron-samx6i.dtsi | 604 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | am437x-sbc-t43.dts | 60 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
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| H A D | am437x-sk-evm.dts | 372 AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
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| H A D | am43x-epos-evm.dts | 433 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
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| H A D | am437x-gp-evm.dts | 293 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
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| /linux/drivers/gpu/drm/nouveau/dispnv04/i2c/ |
| H A D | ch7006_mode.c | 122 .flags = DRM_MODE_FLAG_##hsynp##HSYNC | \
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| /linux/drivers/pinctrl/renesas/ |
| H A D | pfc-sh7786.c | 524 GPIO_FN(HSYNC),
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| /linux/drivers/video/fbdev/ |
| H A D | sstfb.c | 535 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); in sstfb_set_par()
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| /linux/arch/arm/boot/dts/microchip/ |
| H A D | at91sam9g45.dtsi | 283 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
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| /linux/drivers/gpu/drm/ |
| H A D | drm_modes.c | 1742 MODE_STATUS(HSYNC),
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