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Searched refs:GRBM_GFX_INDEX (Results 1 – 25 of 29) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c290 inst_index = REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_INDEX); in imu_v12_0_grbm_gfx_index_remap()
295 val = REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES) << 18 | in imu_v12_0_grbm_gfx_index_remap()
296 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES) << 19 | in imu_v12_0_grbm_gfx_index_remap()
297 REG_GET_FIELD(data, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES) << 20 | in imu_v12_0_grbm_gfx_index_remap()
298 REG_GET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX) << 21 | in imu_v12_0_grbm_gfx_index_remap()
299 REG_GET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX) << 25 | in imu_v12_0_grbm_gfx_index_remap()
H A Damdgpu_amdkfd_gfx_v12.c174 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12()
176 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12()
178 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v12()
H A Dgfx_v9_4.c98 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_select_se_sh()
101 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_select_se_sh()
105 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
108 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
111 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
114 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
H A Damdgpu_amdkfd_gfx_v8.c553 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
555 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
557 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
H A Damdgpu_amdkfd_gfx_v10_3.c600 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
602 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
604 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
H A Damdgpu_amdkfd_gfx_v11.c585 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
589 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
H A Damdgpu_amdkfd_gfx_v10.c688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
690 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
692 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
H A Dgfx_v9_4_2.c853 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_2_select_se_sh()
856 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_2_select_se_sh()
860 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh()
863 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_2_select_se_sh()
866 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh()
869 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
H A Damdgpu_amdkfd_gfx_v9.c638 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
640 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
642 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
H A Dsoc15_common.h158 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \
H A Dgfx_v9_4_3.c695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_3_xcc_select_se_sh()
708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_3_xcc_select_se_sh()
H A Dvce_v3_0.c636 * GRBM_GFX_INDEX.INSTANCE_INDEX is used to specify which VCE in vce_v3_0_check_soft_reset()
848 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
H A Dgfx_v12_0.c1668 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v12_0_select_se_sh()
1671 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v12_0_select_se_sh()
1675 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v12_0_select_se_sh()
1678 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v12_0_select_se_sh()
1681 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, in gfx_v12_0_select_se_sh()
1684 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v12_0_select_se_sh()
H A Dgfx_v8_0.c3390 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3392 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3395 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3397 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
3400 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3402 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
3568 /* GRBM_GFX_INDEX has a different offset on VI */ in gfx_v8_0_write_harvested_raster_configs()
3574 /* GRBM_GFX_INDEX has a different offset on VI */ in gfx_v8_0_write_harvested_raster_configs()
H A Dgfx_v9_0.c2505 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2507 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v9_0_select_se_sh()
2510 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2512 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
2515 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2517 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
H A Dgfx_v6_0.c1310 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v6_0_select_se_sh()
1312 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v6_0_select_se_sh()
1457 /* GRBM_GFX_INDEX has a different offset on SI */ in gfx_v6_0_write_harvested_raster_configs()
1462 /* GRBM_GFX_INDEX has a different offset on SI */ in gfx_v6_0_write_harvested_raster_configs()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcik_regs.h69 #define GRBM_GFX_INDEX 0x30800 macro
/linux/drivers/gpu/drm/radeon/
H A Dcypress_dpm.c125 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
152 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
186 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
207 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
H A Dni.c1069 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1089 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1098 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
H A Dnid.h295 #define GRBM_GFX_INDEX 0x802C macro
H A Dsid.h998 #define GRBM_GFX_INDEX 0x802C macro
H A Dcikd.h1627 #define GRBM_GFX_INDEX 0x30800 macro
H A Devergreen.c3464 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3485 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3494 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Dcayman2 0x0000802C GRBM_GFX_INDEX
H A Devergreen2 0x0000802C GRBM_GFX_INDEX

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