Searched refs:DPLL_CTL (Results 1 – 5 of 5) sorted by relevance
| /linux-3.3/arch/arm/mach-omap1/ |
| D | reset.c | 17 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in omap1_restart()
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| D | sram.S | 25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
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| D | board-voiceblue.c | 230 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in voiceblue_restart()
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| D | clock_data.c | 848 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
862 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
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| /linux-3.3/arch/arm/plat-omap/include/plat/ |
| D | hardware.h | 89 #define DPLL_CTL (0xfffecf00) macro
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