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Searched refs:CURCNTR (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_cursor.c310 intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); in i845_cursor_update_arm()
314 intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); in i845_cursor_update_arm()
344 ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
683 * On some platforms writing CURCNTR first will also in i9xx_cursor_update_arm()
685 * Without the CURCNTR write the CURPOS write would in i9xx_cursor_update_arm()
686 * arm itself. Thus we always update CURCNTR before in i9xx_cursor_update_arm()
699 * the CURCNTR write arms the update. in i9xx_cursor_update_arm()
715 intel_de_write_dsb(display, dsb, CURCNTR(display, pipe), cntl); in i9xx_cursor_update_arm()
754 val = intel_de_read(display, CURCNTR(display, plane->pipe)); in i9xx_cursor_get_hw_state()
774 error->ctl = intel_de_read(display, CURCNTR(displa in g4x_cursor_capture_error()
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H A Dintel_cursor_regs.h12 #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) macro
H A Dintel_display.c8306 intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); in i830_disable_pipe()
8308 intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); in i830_disable_pipe()
/linux/drivers/video/fbdev/i810/
H A Di810_regs.h167 #define CURCNTR 0x70080 macro
H A Di810_main.c857 i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR); in i810_init_cursor()
/linux/drivers/gpu/drm/i915/gvt/
H A Dfb_decoder.c356 val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe)); in intel_vgpu_decode_cursor_plane()
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c156 MMIO_D(CURCNTR(dev_priv, PIPE_A)); in iterate_generic_mmio()
157 MMIO_D(CURCNTR(dev_priv, PIPE_B)); in iterate_generic_mmio()
158 MMIO_D(CURCNTR(dev_priv, PIPE_C)); in iterate_generic_mmio()