| /linux/arch/mips/include/asm/mach-ip32/ |
| H A D | kmalloc.h | 7 #define ARCH_DMA_MINALIGN 32 macro
9 #define ARCH_DMA_MINALIGN 128 macro
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| /linux/arch/riscv/mm/ |
| H A D | dma-noncoherent.c | 15 int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
133 WARN_TAINT(!coherent && riscv_cbom_block_size > ARCH_DMA_MINALIGN, in arch_setup_dma_ops()
135 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
137 ARCH_DMA_MINALIGN, riscv_cbom_block_size); in arch_setup_dma_ops()
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| /linux/arch/arm/kernel/ |
| H A D | cacheinfo.c | 42 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; in cache_line_size_cp15()
44 return ARCH_DMA_MINALIGN; in cache_line_size_cp15()
58 return ARCH_DMA_MINALIGN; in cache_line_size()
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| /linux/drivers/usb/core/ |
| H A D | buffer.c | 37 * ARCH_DMA_MINALIGN. in usb_init_pool_max()
39 if (ARCH_DMA_MINALIGN <= 32) in usb_init_pool_max()
41 else if (ARCH_DMA_MINALIGN <= 64) in usb_init_pool_max()
43 else if (ARCH_DMA_MINALIGN <= 128) in usb_init_pool_max()
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| /linux/include/linux/ |
| H A D | cache.h | 178 #ifdef ARCH_DMA_MINALIGN
181 #define ARCH_DMA_MINALIGN __alignof__(unsigned long long) macro
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| H A D | slab.h | 502 * Setting ARCH_DMA_MINALIGN in arch headers allows that.
505 #if ARCH_DMA_MINALIGN > 8 && !defined(ARCH_KMALLOC_MINALIGN)
506 #define ARCH_KMALLOC_MINALIGN ARCH_DMA_MINALIGN
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| /linux/arch/mips/include/asm/mach-tx49xx/ |
| H A D | kmalloc.h | 5 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/mips/include/asm/mach-n64/ |
| H A D | kmalloc.h | 6 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/mips/include/asm/mach-generic/ |
| H A D | kmalloc.h | 10 #define ARCH_DMA_MINALIGN 128 macro
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| /linux/arch/m68k/include/asm/ |
| H A D | cache.h | 12 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/loongarch/include/asm/ |
| H A D | cache.h | 11 #define ARCH_DMA_MINALIGN (16) macro
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| /linux/arch/microblaze/include/asm/ |
| H A D | cache.h | 22 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/hexagon/include/asm/ |
| H A D | cache.h | 15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/arm/include/asm/ |
| H A D | cache.h | 18 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/riscv/include/asm/ |
| H A D | cache.h | 15 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/nios2/include/asm/ |
| H A D | cache.h | 21 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/sh/include/asm/ |
| H A D | cache.h | 21 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/xtensa/include/asm/ |
| H A D | cache.h | 32 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/arch/csky/include/asm/ |
| H A D | cache.h | 11 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/include/crypto/ |
| H A D | algapi.h | 28 #ifdef ARCH_DMA_MINALIGN
29 #define CRYPTO_DMA_ALIGN ARCH_DMA_MINALIGN
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| /linux/drivers/crypto/marvell/octeontx2/ |
| H A D | otx2_cpt_reqmgr.h | 363 * | | padding for ARCH_DMA_MINALIGN | in cn10k_sgv2_info_create()
391 total_mem_len += (ARCH_DMA_MINALIGN - 1) & in cn10k_sgv2_info_create()
404 info->in_buffer = PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); in cn10k_sgv2_info_create()
468 * | | padding for ARCH_DMA_MINALIGN | in otx2_sg_info_create()
499 total_mem_len += (ARCH_DMA_MINALIGN - 1) & in otx2_sg_info_create()
509 info->in_buffer = PTR_ALIGN((u8 *)info + info_len, ARCH_DMA_MINALIGN); in otx2_sg_info_create()
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| /linux/arch/arc/include/asm/ |
| H A D | cache.h | 52 #define ARCH_DMA_MINALIGN SMP_CACHE_BYTES macro
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| /linux/arch/powerpc/include/asm/ |
| H A D | cache.h | 37 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES macro
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| /linux/drivers/counter/ |
| H A D | counter-core.c | 38 unsigned long privdata[] __aligned(ARCH_DMA_MINALIGN);
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| /linux/drivers/gpu/drm/ |
| H A D | drm_managed.c | 53 * Thus we use ARCH_DMA_MINALIGN for data[] which will force the same
56 u8 __aligned(ARCH_DMA_MINALIGN) data[];
|