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Searched refs:xcc_mask (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c45 uint32_t xcc_mask) in gfxhub_v1_2_xcc_setup_vm_pt_regs() argument
50 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_setup_vm_pt_regs()
68 uint32_t xcc_mask; in gfxhub_v1_2_setup_vm_pt_regs() local
70 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); in gfxhub_v1_2_setup_vm_pt_regs()
71 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, xcc_mask); in gfxhub_v1_2_setup_vm_pt_regs()
75 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_gart_aperture_regs() argument
87 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
92 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_init_gart_aperture_regs()
127 uint32_t xcc_mask) in gfxhub_v1_2_xcc_init_system_aperture_regs() argument
133 for_each_inst(i, xcc_mask) { in gfxhub_v1_2_xcc_init_system_aperture_regs()
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H A Dcyan_skillfish_reg_init.c36 adev->gfx.xcc_mask = 1; in cyan_skillfish_reg_base_init()
H A Damdgpu_discovery.c815 adev->gfx.xcc_mask &= in amdgpu_discovery_read_from_harvest_table()
1104 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; in amdgpu_discovery_get_harvest_info()
1408 adev->gfx.xcc_mask = 0; in amdgpu_discovery_reg_base_init()
1506 adev->gfx.xcc_mask |= in amdgpu_discovery_reg_base_init()
2693 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2722 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2752 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2799 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2830 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
2865 adev->gfx.xcc_mask = 1; in amdgpu_discovery_set_ip_blocks()
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H A Damdgpu_gmc.c1623 uint32_t xcc_mask; in amdgpu_gmc_init_acpi_mem_ranges() local
1625 num_xcc = NUM_XCC(adev->gfx.xcc_mask); in amdgpu_gmc_init_acpi_mem_ranges()
1626 xcc_mask = (1U << num_xcc) - 1; in amdgpu_gmc_init_acpi_mem_ranges()
1628 for_each_inst(xcc_id, xcc_mask) { in amdgpu_gmc_init_acpi_mem_ranges()
H A Damdgpu_virt.c1369 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_vfi_reg_rw()
1491 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
H A Dnbio_v7_9.c439 0xff & ~(adev->gfx.xcc_mask)); in nbio_v7_9_init_registers()
H A Damdgpu_vm.h530 uint32_t xcc_mask);
H A Damdgpu_xcp.c640 switch (NUM_XCC(adev->gfx.xcc_mask)) { in amdgpu_xcp_update_supported_modes()
H A Dsdma_v4_4_2.c148 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
153 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1)) in sdma_v4_4_2_irq_id_to_seq()
H A Damdgpu_vm.c1691 uint32_t xcc_mask) in amdgpu_vm_flush_compute_tlb() argument
1711 for_each_inst(xcc, xcc_mask) { in amdgpu_vm_flush_compute_tlb()
H A Dgmc_v9_0.c1932 NUM_XCC(adev->gfx.xcc_mask)); in gmc_v9_0_sw_init()
H A Damdgpu_psp.c1991 ras_cmd->ras_in_message.init_flags.xcc_mask = in psp_ras_initialize()
1992 adev->gfx.xcc_mask; in psp_ras_initialize()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c163 NUM_XCC(node->xcc_mask), in allocate_mqd()
400 *ctl_stack_size = m->cp_hqd_cntl_stack_size * NUM_XCC(mm->dev->xcc_mask); in get_checkpoint_info()
424 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in checkpoint_mqd_v9_4_3()
595 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_hiq_v9_4_3()
622 uint32_t xcc_mask = mm->dev->xcc_mask; in hiq_load_mqd_kiq_v9_4_3() local
627 for_each_inst(xcc_id, xcc_mask) { in hiq_load_mqd_kiq_v9_4_3()
646 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_hiq_mqd_v9_4_3() local
652 for_each_inst(xcc_id, xcc_mask) { in destroy_hiq_mqd_v9_4_3()
672 uint32_t xcc_mask = mm->dev->xcc_mask; in check_preemption_failed_v9_4_3() local
677 for_each_inst(xcc_id, xcc_mask) { in check_preemption_failed_v9_4_3()
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H A Dkfd_mqd_manager_v12_1.c55 int inc = NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask_v12_1()
56 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask_v12_1()
145 mqd_size *= NUM_XCC(node->xcc_mask); in allocate_mqd()
461 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in init_mqd_v12_1()
488 NUM_XCC(mm->dev->xcc_mask); in init_mqd_v12_1()
511 for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { in update_mqd_v12_1()
532 uint32_t xcc_mask = mm->dev->xcc_mask; in destroy_mqd_v12_1() local
541 for_each_inst(xcc_id, xcc_mask) { in destroy_mqd_v12_1()
562 uint32_t xcc_mask = mm->dev->xcc_mask; in load_mqd_v12_1() local
567 for_each_inst(xcc_id, xcc_mask) { in load_mqd_v12_1()
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H A Dkfd_mqd_manager.c82 NUM_XCC(dev->xcc_mask); in allocate_sdma_mqd()
111 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); in mqd_symmetrically_map_cu_mask()
112 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; in mqd_symmetrically_map_cu_mask()
H A Dkfd_device_queue_manager.c149 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_sh_mem_settings() local
152 for_each_inst(xcc_id, xcc_mask) in program_sh_mem_settings()
260 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in add_queue_mes()
291 queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; in remove_queue_mes()
523 uint32_t xcc_mask = dqm->dev->xcc_mask; in program_trap_handler_settings() local
527 for_each_inst(xcc_id, xcc_mask) in program_trap_handler_settings()
797 uint32_t xcc_mask = dev->xcc_mask; in dbgdev_wave_reset_wavefronts() local
844 for_each_inst(xcc_id, xcc_mask) in dbgdev_wave_reset_wavefronts()
1472 uint32_t xcc_mask = dqm->dev->xcc_mask; in set_pasid_vmid_mapping() local
1475 for_each_inst(xcc_id, xcc_mask) { in set_pasid_vmid_mapping()
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H A Dkfd_device.c684 uint32_t xcc_mask = node->xcc_mask; in kfd_setup_interrupt_bitmap() local
710 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
719 for_each_inst(xcc, xcc_mask) { in kfd_setup_interrupt_bitmap()
880 &node->xcc_mask); in kgd2kfd_device_init()
883 node->xcc_mask = in kgd2kfd_device_init()
884 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; in kgd2kfd_device_init()
H A Dkfd_queue.c312 topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_acquire_buffers()
359 topo_dev->node_props.debug_memory_size) * NUM_XCC(pdd->dev->xcc_mask); in kfd_queue_release_buffers()
492 cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); in kfd_queue_ctx_save_restore_size()
H A Dkfd_debug.c378 ffs(pdd->dev->xcc_mask) - 1); in kfd_dbg_set_mes_debug_mode()
471 uint32_t xcc_mask = pdd->dev->xcc_mask; in kfd_dbg_trap_set_dev_address_watch() local
488 for_each_inst(xcc_id, xcc_mask) in kfd_dbg_trap_set_dev_address_watch()
1122 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); in kfd_dbg_trap_device_snapshot()
H A Dkfd_topology.c463 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()
543 NUM_XCC(dev->gpu->xcc_mask)); in node_show()
1108 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16); in kfd_generate_gpu_id()
1687 int num_xcc = NUM_XCC(knode->xcc_mask); in fill_in_l2_l3_pcache()
1693 start = ffs(knode->xcc_mask) - 1; in fill_in_l2_l3_pcache()
1818 start = ffs(kdev->xcc_mask) - 1; in kfd_fill_cache_non_crat_info()
1819 end = start + NUM_XCC(kdev->xcc_mask); in kfd_fill_cache_non_crat_info()
H A Dkfd_process_queue_manager.c98 ffs(pdd->dev->xcc_mask) - 1); in kfd_process_dequeue_from_device()
1042 set_queue_properties_from_criu(&qp, q_data, NUM_XCC(pdd->dev->adev->gfx.xcc_mask)); in kfd_criu_restore_queue()
1118 num_xccs = NUM_XCC(q->device->xcc_mask); in pqm_debugfs_mqds()
H A Dkfd_priv.h279 uint32_t xcc_mask; /* Instance mask of XCCs present */ member
1559 amdgpu_vm_flush_compute_tlb(adev, vm, type, pdd->dev->xcc_mask); in kfd_flush_tlb()
H A Dkfd_process.c306 &max_waves_per_cu, ffs(dev->xcc_mask) - 1); in kfd_get_cu_occupancy()
316 wave_cnt += (NUM_XCC(dev->xcc_mask) * in kfd_get_cu_occupancy()
/linux/drivers/gpu/drm/amd/ras/ras_mgr/
H A Damdgpu_ras_mgr.c215 ras_ta_param->xcc_mask = adev->gfx.xcc_mask; in amdgpu_ras_mgr_get_ras_ta_init_param()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_12_ppt.c947 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { in smu_v13_0_12_get_gpu_metrics()

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