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Searched refs:wrmsrq (Results 1 – 25 of 88) sorted by relevance

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/linux/arch/x86/kernel/
H A Dfred.c47 wrmsrq(MSR_IA32_FRED_CONFIG, in cpu_init_fred_exceptions()
53 wrmsrq(MSR_IA32_FRED_STKLVLS, 0); in cpu_init_fred_exceptions()
59 wrmsrq(MSR_IA32_FRED_RSP0, __this_cpu_read(fred_rsp0)); in cpu_init_fred_exceptions()
61 wrmsrq(MSR_IA32_FRED_RSP1, 0); in cpu_init_fred_exceptions()
62 wrmsrq(MSR_IA32_FRED_RSP2, 0); in cpu_init_fred_exceptions()
63 wrmsrq(MSR_IA32_FRED_RSP3, 0); in cpu_init_fred_exceptions()
83 wrmsrq(MSR_IA32_FRED_STKLVLS, in cpu_init_fred_rsps()
90 wrmsrq(MSR_IA32_FRED_RSP1, __this_cpu_ist_top_va(DB)); in cpu_init_fred_rsps()
91 wrmsrq(MSR_IA32_FRED_RSP2, __this_cpu_ist_top_va(NMI)); in cpu_init_fred_rsps()
92 wrmsrq(MSR_IA32_FRED_RSP3, __this_cpu_ist_top_va(DF)); in cpu_init_fred_rsps()
H A Dshstk.c176 wrmsrq(MSR_IA32_PL3_SSP, addr + size); in shstk_setup()
177 wrmsrq(MSR_IA32_U_CET, CET_SHSTK_EN); in shstk_setup()
263 wrmsrq(MSR_IA32_PL3_SSP, ssp + SS_FRAME_SIZE); in shstk_pop()
283 wrmsrq(MSR_IA32_PL3_SSP, ssp); in shstk_push()
416 wrmsrq(MSR_IA32_PL3_SSP, ssp); in setup_signal_shadow_stack()
440 wrmsrq(MSR_IA32_PL3_SSP, ssp); in restore_signal_shadow_stack()
517 wrmsrq(MSR_IA32_U_CET, msrval); in wrss_control()
536 wrmsrq(MSR_IA32_U_CET, 0); in shstk_disable()
537 wrmsrq(MSR_IA32_PL3_SSP, 0); in shstk_disable()
H A Dkvm.c319 wrmsrq(MSR_KVM_ASYNC_PF_ACK, 1); in DEFINE_IDTENTRY_SYSVEC()
345 wrmsrq(MSR_KVM_STEAL_TIME, (slow_virt_to_phys(st) | KVM_MSR_ENABLED)); in kvm_register_steal_time()
379 wrmsrq(MSR_KVM_ASYNC_PF_INT, HYPERVISOR_CALLBACK_VECTOR); in kvm_guest_cpu_init()
381 wrmsrq(MSR_KVM_ASYNC_PF_EN, pa); in kvm_guest_cpu_init()
394 wrmsrq(MSR_KVM_PV_EOI_EN, pa); in kvm_guest_cpu_init()
406 wrmsrq(MSR_KVM_ASYNC_PF_EN, 0); in kvm_pv_disable_apf()
417 wrmsrq(MSR_KVM_STEAL_TIME, 0); in kvm_disable_steal_time()
469 wrmsrq(MSR_KVM_PV_EOI_EN, 0); in kvm_guest_cpu_offline()
471 wrmsrq(MSR_KVM_MIGRATION_CONTROL, 0); in kvm_guest_cpu_offline()
633 wrmsrq(MSR_KVM_MIGRATION_CONTROL, KVM_MIGRATION_READY); in setup_efi_kvm_sev_migration()
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H A Dtsc_sync.c74 wrmsrq(MSR_IA32_TSC_ADJUST, adj->adjusted); in tsc_verify_tsc_adjust()
146 wrmsrq(MSR_IA32_TSC_ADJUST, 0); in tsc_sanitize_first_cpu()
233 wrmsrq(MSR_IA32_TSC_ADJUST, ref->adjusted); in tsc_store_and_check_tsc_adjust()
522 wrmsrq(MSR_IA32_TSC_ADJUST, cur->adjusted); in check_tsc_sync_target()
H A Dprocess.c355 wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval); in set_cpuid_faulting()
583 wrmsrq(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
600 wrmsrq(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
610 wrmsrq(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
619 wrmsrq(MSR_AMD64_LS_CFG, msr); in amd_set_core_ssb_state()
629 wrmsrq(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn)); in amd_set_ssb_virt_state()
736 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); in __switch_to_xtra()
/linux/arch/x86/hyperv/
H A Dhv_init.c170 wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_init()
201 wrmsrq(HV_X64_MSR_TSC_EMULATION_STATUS, *(u64 *)&emu_status); in hyperv_stop_tsc_emulation()
249 wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in set_hv_tscchange_cb()
250 wrmsrq(HV_X64_MSR_TSC_EMULATION_CONTROL, *((u64 *)&emu_ctrl)); in set_hv_tscchange_cb()
265 wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *(u64 *)&re_ctrl); in clear_hv_tscchange_cb()
303 wrmsrq(HV_X64_MSR_VP_ASSIST_PAGE, msr.as_uint64); in hv_cpu_die()
323 wrmsrq(HV_X64_MSR_REENLIGHTENMENT_CONTROL, *((u64 *)&re_ctrl)); in hv_cpu_die()
382 wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_suspend()
401 wrmsrq(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); in hv_resume()
516 wrmsrq(HV_X64_MSR_GUEST_OS_ID, guest_id); in hyperv_init()
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H A Dhv_apic.c53 wrmsrq(HV_X64_MSR_ICR, reg_val); in hv_apic_icr_write()
84 wrmsrq(HV_X64_MSR_EOI, val); in hv_apic_write()
87 wrmsrq(HV_X64_MSR_TPR, val); in hv_apic_write()
101 wrmsrq(HV_X64_MSR_EOI, APIC_EOI_ACK); in hv_apic_eoi_write()
/linux/arch/x86/events/intel/
H A Duncore_nhmex.c204 wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); in nhmex_uncore_msr_init_box()
209 wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, 0); in nhmex_uncore_msr_exit_box()
223 wrmsrq(msr, config); in nhmex_uncore_msr_disable_box()
238 wrmsrq(msr, config); in nhmex_uncore_msr_enable_box()
244 wrmsrq(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
252 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
254 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
256 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
386 wrmsrq(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
387 wrmsrq(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
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H A Dlbr.c141 wrmsrq(MSR_LBR_SELECT, lbr_select); in __intel_pmu_lbr_enable()
159 wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); in __intel_pmu_lbr_enable()
162 wrmsrq(MSR_ARCH_LBR_CTL, lbr_select | ARCH_LBR_CTL_LBREN); in __intel_pmu_lbr_enable()
170 wrmsrq(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_32()
178 wrmsrq(x86_pmu.lbr_from + i, 0); in intel_pmu_lbr_reset_64()
179 wrmsrq(x86_pmu.lbr_to + i, 0); in intel_pmu_lbr_reset_64()
181 wrmsrq(x86_pmu.lbr_info + i, 0); in intel_pmu_lbr_reset_64()
188 wrmsrq(MSR_ARCH_LBR_DEPTH, x86_pmu.lbr_nr); in intel_pmu_arch_lbr_reset()
203 wrmsrq(MSR_LBR_SELECT, 0); in intel_pmu_lbr_reset()
286 wrmsrq(x86_pmu.lbr_from + idx, val); in wrlbr_from()
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H A Dknc.c165 wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_disable_all()
174 wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_CTRL, val); in knc_pmu_enable_all()
211 wrmsrq(MSR_KNC_IA32_PERF_GLOBAL_OVF_CONTROL, ack); in knc_pmu_ack_status()
/linux/arch/x86/kernel/cpu/
H A Dtsx.c51 wrmsrq(MSR_IA32_TSX_CTRL, tsx); in tsx_disable()
70 wrmsrq(MSR_IA32_TSX_CTRL, tsx); in tsx_enable()
131 wrmsrq(MSR_TSX_FORCE_ABORT, msr); in tsx_clear_cpuid()
135 wrmsrq(MSR_IA32_TSX_CTRL, msr); in tsx_clear_cpuid()
164 wrmsrq(MSR_IA32_MCU_OPT_CTRL, mcu_opt_ctrl); in tsx_dev_mode_disable()
H A Dcommon.c612 wrmsrq(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); in ibt_save()
626 wrmsrq(MSR_IA32_S_CET, msr); in ibt_restore()
650 wrmsrq(MSR_IA32_S_CET, CET_ENDBR_EN); in setup_cet()
652 wrmsrq(MSR_IA32_S_CET, 0); in setup_cet()
658 wrmsrq(MSR_IA32_S_CET, 0); in setup_cet()
669 wrmsrq(MSR_IA32_S_CET, 0); in cet_disable()
670 wrmsrq(MSR_IA32_U_CET, 0); in cet_disable()
809 wrmsrq(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); in switch_gdt_and_percpu_base()
1919 wrmsrq(MSR_FS_BASE, 1); in detect_null_seg_behavior()
1922 wrmsrq(MSR_FS_BASE, old_base); in detect_null_seg_behavior()
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H A Dbus_lock.c150 wrmsrq(MSR_TEST_CTRL, msr_test_ctrl_cache); in __split_lock_setup()
167 wrmsrq(MSR_TEST_CTRL, test_ctrl_val); in sld_update_msr()
316 wrmsrq(MSR_IA32_DEBUGCTLMSR, val); in bus_lock_init()
/linux/arch/x86/kernel/cpu/mce/
H A Dinject.c479 wrmsrq(MSR_IA32_MCG_STATUS, m.mcgstatus); in prepare_msrs()
483 wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); in prepare_msrs()
484 wrmsrq(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); in prepare_msrs()
486 wrmsrq(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); in prepare_msrs()
487 wrmsrq(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); in prepare_msrs()
490 wrmsrq(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); in prepare_msrs()
493 wrmsrq(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); in prepare_msrs()
495 wrmsrq(MSR_IA32_MCx_STATUS(b), m.status); in prepare_msrs()
496 wrmsrq(MSR_IA32_MCx_ADDR(b), m.addr); in prepare_msrs()
499 wrmsrq(MSR_IA32_MCx_MISC(b), m.misc); in prepare_msrs()
H A Dintel.c146 wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
235 wrmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_claim_bank()
329 wrmsrq(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
436 wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
448 wrmsrq(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
/linux/arch/x86/power/
H A Dcpu.c60 wrmsrq(msr->info.msr_no, msr->info.reg.q); in msr_restore_context()
202 wrmsrq(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); in __restore_processor_state()
212 wrmsrq(MSR_EFER, ctxt->efer); in __restore_processor_state()
235 wrmsrq(MSR_GS_BASE, ctxt->kernelmode_gs_base); in __restore_processor_state()
271 wrmsrq(MSR_FS_BASE, ctxt->fs_base); in __restore_processor_state()
272 wrmsrq(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); in __restore_processor_state()
/linux/arch/x86/kvm/svm/
H A Dpmu.c245 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, global_status); in amd_mediated_pmu_load()
247 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, pmu->global_status); in amd_mediated_pmu_load()
248 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, pmu->global_ctrl); in amd_mediated_pmu_load()
255 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); in amd_mediated_pmu_put()
260 wrmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, pmu->global_status); in amd_mediated_pmu_put()
/linux/arch/x86/events/amd/
H A Dlbr.c65 wrmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2, val); in amd_pmu_lbr_set_from()
70 wrmsrq(MSR_AMD_SAMP_BR_FROM + idx * 2 + 1, val); in amd_pmu_lbr_set_to()
337 wrmsrq(MSR_AMD64_LBR_SELECT, 0); in amd_pmu_lbr_reset()
400 wrmsrq(MSR_AMD64_LBR_SELECT, lbr_select); in amd_pmu_lbr_enable_all()
405 wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); in amd_pmu_lbr_enable_all()
409 wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN); in amd_pmu_lbr_enable_all()
/linux/drivers/video/fbdev/geode/
H A Dvideo_gx.c154 wrmsrq(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
162 wrmsrq(MSR_GLCP_SYS_RSTPLL, sys_rstpll); in gx_set_dclk_frequency()
166 wrmsrq(MSR_GLCP_DOTPLL, dotpll); in gx_set_dclk_frequency()
186 wrmsrq(MSR_GX_MSR_PADSEL, val); in gx_configure_tft()
/linux/arch/x86/xen/
H A Dsuspend.c43 wrmsrq(MSR_IA32_SPEC_CTRL, this_cpu_read(spec_ctrl)); in xen_vcpu_notify_restore()
61 wrmsrq(MSR_IA32_SPEC_CTRL, 0); in xen_vcpu_notify_suspend()
/linux/drivers/cpufreq/
H A Dlonghaul.c147 wrmsrq(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
156 wrmsrq(MSR_VIA_BCR2, bcr2.val); in do_longhaul1()
183 wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
197 wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
202 wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
215 wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
220 wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
234 wrmsrq(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver()
/linux/arch/x86/kernel/cpu/resctrl/
H A Drdtgroup.c115 wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config); in resctrl_arch_mon_event_config_write()
122 wrmsrq(MSR_IA32_L3_QOS_CFG, *enable ? L3_QOS_CDP_ENABLE : 0ULL); in l3_qos_cfg_update()
129 wrmsrq(MSR_IA32_L2_QOS_CFG, *enable ? L2_QOS_CDP_ENABLE : 0ULL); in l2_qos_cfg_update()
H A Dpseudo_lock.c218 wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr); in resctrl_arch_pseudo_lock_fn()
254 wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); in resctrl_arch_measure_cycles_lat_fn()
350 wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); in measure_residency_fn()
/linux/drivers/platform/x86/intel/ifs/
H A Dload.c131 wrmsrq(msrs->copy_hashes, ifs_hash_ptr); in copy_hashes_authenticate_chunks()
153 wrmsrq(msrs->copy_chunks, linear_addr); in copy_hashes_authenticate_chunks()
199 wrmsrq(msrs->copy_hashes, ifs_hash_ptr); in copy_hashes_authenticate_chunks_gen2()
220 wrmsrq(msrs->test_ctrl, INVALIDATE_STRIDE); in copy_hashes_authenticate_chunks_gen2()
242 wrmsrq(msrs->copy_chunks, (u64)chunk_table); in copy_hashes_authenticate_chunks_gen2()
/linux/arch/x86/events/zhaoxin/
H A Dcore.c258 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0); in zhaoxin_pmu_disable_all()
263 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); in zhaoxin_pmu_enable_all()
277 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); in zhaoxin_pmu_ack_status()
299 wrmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
336 wrmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()

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