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Searched refs:writer_wm_sets (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c496 if (ranges->writer_wm_sets[i].wm_inst > 3) in pp_rv_set_wm_ranges()
500 ranges->writer_wm_sets[i].wm_inst; in pp_rv_set_wm_ranges()
502 ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
504 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
506 ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
508 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000; in pp_rv_set_wm_ranges()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c504 ranges->writer_wm_sets[0].wm_inst = WM_A; in build_watermark_ranges()
505 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()
506 ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in build_watermark_ranges()
507 ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()
508 ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in build_watermark_ranges()
/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1397 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1398 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1399 ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1400 ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1401 ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000; in dcn_bw_notify_pplib_of_wm_ranges()
1409 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1410 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200; in dcn_bw_notify_pplib_of_wm_ranges()
1411 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()
1412 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800; in dcn_bw_notify_pplib_of_wm_ranges()
1413 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000; in dcn_bw_notify_pplib_of_wm_ranges()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c443 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
445 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
447 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in smu_v13_0_5_set_watermarks_table()
449 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in smu_v13_0_5_set_watermarks_table()
452 clock_ranges->writer_wm_sets[i].wm_inst; in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c699 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
701 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
703 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in smu_v13_0_4_set_watermarks_table()
705 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in smu_v13_0_4_set_watermarks_table()
708 clock_ranges->writer_wm_sets[i].wm_inst; in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c534 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()
536 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in yellow_carp_set_watermarks_table()
538 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in yellow_carp_set_watermarks_table()
540 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in yellow_carp_set_watermarks_table()
543 clock_ranges->writer_wm_sets[i].wm_inst; in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1085 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()
1087 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in renoir_set_watermarks_table()
1089 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in renoir_set_watermarks_table()
1091 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in renoir_set_watermarks_table()
1094 clock_ranges->writer_wm_sets[i].wm_inst; in renoir_set_watermarks_table()
1096 clock_ranges->writer_wm_sets[i].wm_type; in renoir_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c603 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in smu_v15_0_0_set_watermarks_table()
605 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in smu_v15_0_0_set_watermarks_table()
607 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in smu_v15_0_0_set_watermarks_table()
609 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in smu_v15_0_0_set_watermarks_table()
612 clock_ranges->writer_wm_sets[i].wm_inst; in smu_v15_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h94 struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c516 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
518 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
520 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
522 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
525 clock_ranges->writer_wm_sets[i].wm_inst; in smu_v14_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1389 ranges.writer_wm_sets[0].wm_inst = 0; in set_wm_ranges()
1390 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1391 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1392 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1393 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c1628 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()
1630 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in vangogh_set_watermarks_table()
1632 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in vangogh_set_watermarks_table()
1634 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in vangogh_set_watermarks_table()
1637 clock_ranges->writer_wm_sets[i].wm_inst; in vangogh_set_watermarks_table()
H A Dnavi10_ppt.c1945 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()
1947 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in navi10_set_watermarks_table()
1949 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in navi10_set_watermarks_table()
1951 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in navi10_set_watermarks_table()
1954 clock_ranges->writer_wm_sets[i].wm_inst; in navi10_set_watermarks_table()
H A Dsienna_cichlid_ppt.c1861 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1863 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
1865 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1867 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; in sienna_cichlid_set_watermarks_table()
1870 clock_ranges->writer_wm_sets[i].wm_inst; in sienna_cichlid_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c2633 ranges.writer_wm_sets[0].wm_inst = 0; in dcn20_resource_construct()
2634 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2635 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2636 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2637 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()