| /linux/arch/arc/plat-hsdk/ |
| H A D | platform.c | 209 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
210 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
211 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
212 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
213 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0)); in hsdk_init_memory_bridge_axi_dmac()
215 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
216 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
217 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
218 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
219 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1)); in hsdk_init_memory_bridge_axi_dmac()
[all …]
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| /linux/drivers/phy/qualcomm/ |
| H A D | phy-qcom-edp.c | 249 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | in qcom_edp_phy_init()
257 writel(DP_PHY_PD_CTL_PSR_PWRDN, edp->edp + DP_PHY_PD_CTL); in qcom_edp_phy_init()
260 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | in qcom_edp_phy_init()
273 writel(0xfc, edp->edp + DP_PHY_MODE); in qcom_edp_phy_init()
276 writel(aux_cfg[i], edp->edp + DP_PHY_AUX_CFG(i)); in qcom_edp_phy_init()
278 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | in qcom_edp_phy_init()
326 writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
327 writel(swing, edp->tx0 + TXn_TX_DRV_LVL); in qcom_edp_set_voltages()
328 writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); in qcom_edp_set_voltages()
330 writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); in qcom_edp_set_voltages()
[all …]
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| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_20nm.c | 15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
22 writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8, in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
30 writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail), in dsi_20nm_dphy_set_timing()
32 writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst), in dsi_20nm_dphy_set_timing()
34 writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) | in dsi_20nm_dphy_set_timing()
[all …]
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| H A D | dsi_phy_28nm.c | 108 writel(DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET, base + REG_DSI_28nm_PHY_PLL_TEST_CFG); in pll_28nm_software_reset()
110 writel(0, base + REG_DSI_28nm_PHY_PLL_TEST_CFG); in pll_28nm_software_reset()
133 writel(3, base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG); in dsi_pll_28nm_clk_set_rate()
144 writel(lpfr_lut[i].resistance, base + REG_DSI_28nm_PHY_PLL_LPFR_CFG); in dsi_pll_28nm_clk_set_rate()
147 writel(0x70, base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG); in dsi_pll_28nm_clk_set_rate()
148 writel(0x15, base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG); in dsi_pll_28nm_clk_set_rate()
200 writel(0x02, base + REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG); in dsi_pll_28nm_clk_set_rate()
201 writel(0x2b, base + REG_DSI_28nm_PHY_PLL_CAL_CFG3); in dsi_pll_28nm_clk_set_rate()
202 writel(0x06, base + REG_DSI_28nm_PHY_PLL_CAL_CFG4); in dsi_pll_28nm_clk_set_rate()
203 writel(0x0d, base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2); in dsi_pll_28nm_clk_set_rate()
[all …]
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| H A D | dsi_phy_28nm_8960.c | 107 writel(fb_divider & 0xff, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1); in dsi_pll_28nm_clk_set_rate()
113 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_2); in dsi_pll_28nm_clk_set_rate()
119 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_set_rate()
121 writel(0xf, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_6); in dsi_pll_28nm_clk_set_rate()
125 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_clk_set_rate()
201 writel(val, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_8); in dsi_pll_28nm_vco_prepare()
204 writel(DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE, in dsi_pll_28nm_vco_prepare()
229 writel(0x00, pll_28nm->phy->pll_base + REG_DSI_28nm_8960_PHY_PLL_CTRL_0); in dsi_pll_28nm_vco_unprepare()
324 writel(val, bytediv->reg); in clk_bytediv_set_rate()
370 writel(cached_state->postdiv3, base + REG_DSI_28nm_8960_PHY_PLL_CTRL_10); in dsi_28nm_pll_restore_state()
[all …]
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| H A D | dsi_phy_10nm.c | 191 writel(config->ssc_stepsize & 0xff, in dsi_pll_ssc_commit()
193 writel(config->ssc_stepsize >> 8, in dsi_pll_ssc_commit()
195 writel(config->ssc_div_per & 0xff, in dsi_pll_ssc_commit()
197 writel(config->ssc_div_per >> 8, in dsi_pll_ssc_commit()
199 writel(config->ssc_adj_per & 0xff, in dsi_pll_ssc_commit()
201 writel(config->ssc_adj_per >> 8, in dsi_pll_ssc_commit()
203 writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0), in dsi_pll_ssc_commit()
212 writel(0x80, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE); in dsi_pll_config_hzindep_reg()
213 writel(0x03, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO); in dsi_pll_config_hzindep_reg()
214 writel(0x00, base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE); in dsi_pll_config_hzindep_reg()
[all …]
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| H A D | dsi_phy_7nm.c | 245 writel(config->ssc_stepsize & 0xff, in dsi_pll_ssc_commit()
247 writel(config->ssc_stepsize >> 8, in dsi_pll_ssc_commit()
249 writel(config->ssc_div_per & 0xff, in dsi_pll_ssc_commit()
251 writel(config->ssc_div_per >> 8, in dsi_pll_ssc_commit()
253 writel(config->ssc_adj_per & 0xff, in dsi_pll_ssc_commit()
255 writel(config->ssc_adj_per >> 8, in dsi_pll_ssc_commit()
257 writel(SSC_EN | (config->ssc_center ? SSC_CENTER : 0), in dsi_pll_ssc_commit()
294 writel(analog_controls_five_1, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1); in dsi_pll_config_hzindep_reg()
295 writel(vco_config_1, base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1); in dsi_pll_config_hzindep_reg()
296 writel(0x01, base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE); in dsi_pll_config_hzindep_reg()
[all …]
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| /linux/drivers/video/fbdev/via/ |
| H A D | accel.c | 34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
91 writel(tmp, engine + 0x08); in hw_bitblt_1()
100 writel(tmp, engine + 0x0C); in hw_bitblt_1()
108 writel(tmp, engine + 0x10); in hw_bitblt_1()
111 writel(fg_color, engine + 0x18); in hw_bitblt_1()
114 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
124 writel(tmp, engine + 0x30); in hw_bitblt_1()
133 writel(tmp, engine + 0x34); in hw_bitblt_1()
145 writel(tmp, engine + 0x38); in hw_bitblt_1()
158 writel(ge_cmd, engine); in hw_bitblt_1()
[all …]
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| /linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | analogix_dp_reg.c | 34 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
38 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
48 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
62 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); in analogix_dp_lane_swap()
70 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); in analogix_dp_init_analog_param()
73 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); in analogix_dp_init_analog_param()
80 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); in analogix_dp_init_analog_param()
81 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); in analogix_dp_init_analog_param()
82 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); in analogix_dp_init_analog_param()
83 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); in analogix_dp_init_analog_param()
[all …]
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| /linux/drivers/net/ethernet/chelsio/cxgb/ |
| H A D | espi.c | 56 writel(V_WRITE_DATA(wr_data) | in tricn_write()
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
83 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
102 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, in tricn_init()
120 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
127 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
135 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
136 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
[all …]
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| H A D | tp.c | 32 writel(val, ap->regs + A_TP_IN_CONFIG); in tp_init()
33 writel(F_TP_OUT_CSPI_CPL | in tp_init()
37 writel(V_IP_TTL(64) | in tp_init()
47 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | in tp_init()
78 writel(0xffffffff, in t1_tp_intr_enable()
80 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_enable()
86 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable()
87 writel(tp_intr | F_PL_INTR_TP, in t1_tp_intr_enable()
99 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_disable()
100 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_disable()
[all …]
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| /linux/drivers/video/fbdev/ |
| H A D | wmt_ge_rops.c | 89 writel(p->var.bits_per_pixel == 32 ? 3 : in wmt_ge_fillrect()
91 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); in wmt_ge_fillrect()
92 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); in wmt_ge_fillrect()
93 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); in wmt_ge_fillrect()
94 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); in wmt_ge_fillrect()
95 writel(rect->dx, regbase + GE_DESTAREAX_OFF); in wmt_ge_fillrect()
96 writel(rect->dy, regbase + GE_DESTAREAY_OFF); in wmt_ge_fillrect()
97 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); in wmt_ge_fillrect()
98 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); in wmt_ge_fillrect()
100 writel(pat, regbase + GE_PAT0C_OFF); in wmt_ge_fillrect()
[all …]
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| /linux/drivers/media/platform/samsung/s5p-jpeg/ |
| H A D | jpeg-hw-exynos3250.c | 23 writel(1, regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
35 writel(1, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
41 writel(0, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
46 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON); in exynos3250_jpeg_poweron()
51 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) & in exynos3250_jpeg_set_dma_num()
66 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
117 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_input_raw_fmt()
129 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_set_y16()
143 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_proc_mode()
165 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_subsampling_mode()
[all …]
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| H A D | jpeg-hw-exynos4.c | 21 writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
39 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
43 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
47 writel(reg & EXYNOS4_ENC_DEC_MODE_MASK, in exynos4_jpeg_set_enc_dec_mode()
133 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_img_fmt()
166 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_enc_out_fmt()
175 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt()
179 writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt()
[all …]
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| /linux/drivers/ata/ |
| H A D | ahci_qoriq.c | 134 writel(px_cmd, port_mmio + PORT_CMD); in ahci_qoriq_hardreset()
138 writel(px_is, port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
174 writel(SATA_ECC_DISABLE, qpriv->ecc_addr); in ahci_qoriq_phy_init()
175 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
176 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); in ahci_qoriq_phy_init()
177 writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); in ahci_qoriq_phy_init()
178 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); in ahci_qoriq_phy_init()
179 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); in ahci_qoriq_phy_init()
180 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init()
182 writel(AHCI_PORT_AXICC_CFG, in ahci_qoriq_phy_init()
[all …]
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| /linux/drivers/scsi/bfa/ |
| H A D | bfa_ioc_ct.c | 66 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
68 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
69 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
88 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
97 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
99 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock()
117 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
121 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock()
131 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
132 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
[all …]
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| /linux/drivers/net/ethernet/brocade/bna/ |
| H A D | bfa_ioc_ct.c | 131 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
133 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock()
157 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock()
182 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock()
191 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail()
192 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail()
419 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
429 writel(1, ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat()
452 writel(r32 & __MSIX_VT_OFST_, in bfa_nw_ioc_ct2_poweron()
457 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | in bfa_nw_ioc_ct2_poweron()
[all …]
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| /linux/drivers/media/platform/samsung/s5p-mfc/ |
| H A D | s5p_mfc_opr_v6.c | 35 #undef writel
36 #define writel(v, r) \ macro
597 writel(strm_size, mfc_regs->d_stream_data_size); in s5p_mfc_set_dec_stream_buffer_v6()
598 writel(buf_addr, mfc_regs->d_cpb_buffer_addr); in s5p_mfc_set_dec_stream_buffer_v6()
599 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); in s5p_mfc_set_dec_stream_buffer_v6()
600 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); in s5p_mfc_set_dec_stream_buffer_v6()
624 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); in s5p_mfc_set_dec_frame_buffer_v6()
625 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
626 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
629 writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6()
[all …]
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| /linux/sound/soc/ux500/ |
| H A D | ux500_msp_i2s.c | 138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
262 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
292 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel()
295 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
297 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
[all …]
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| /linux/sound/soc/pxa/ |
| H A D | pxa2xx-i2s.c | 103 writel(0, i2s_reg_base + SACR0); in pxa2xx_i2s_startup()
175 writel(0, i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0); in pxa2xx_i2s_hw_params()
180 writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1); in pxa2xx_i2s_hw_params()
183 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
185 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR); in pxa2xx_i2s_hw_params()
189 writel(0x48, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
192 writel(0x34, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
195 writel(0x24, i2s_reg_base + SADIV); in pxa2xx_i2s_hw_params()
[all …]
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| /linux/drivers/net/ethernet/sunplus/ |
| H A D | spl2sw_mac.c | 22 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_mac_hw_stop()
23 writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0); in spl2sw_mac_hw_stop()
28 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_stop()
34 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_stop()
45 writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL); in spl2sw_mac_hw_start()
50 writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0); in spl2sw_mac_hw_start()
60 writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8), in spl2sw_mac_addr_add()
62 writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) + in spl2sw_mac_addr_add()
69 writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0); in spl2sw_mac_addr_add()
95 writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8), in spl2sw_mac_addr_del()
[all …]
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| /linux/drivers/gpu/drm/mxsfb/ |
| H A D | lcdif_kms.c | 173 writel(DISP_PARA_LINE_PATTERN_RGB565, in lcdif_set_formats()
177 writel(DISP_PARA_LINE_PATTERN_RGB888, in lcdif_set_formats()
181 writel(DISP_PARA_LINE_PATTERN_UYVY_H, in lcdif_set_formats()
193 writel(CTRLDESCL0_5_BPP_16_RGB565, in lcdif_set_formats()
197 writel(CTRLDESCL0_5_BPP_24_RGB888, in lcdif_set_formats()
201 writel(CTRLDESCL0_5_BPP_16_ARGB1555, in lcdif_set_formats()
205 writel(CTRLDESCL0_5_BPP_16_ARGB4444, in lcdif_set_formats()
209 writel(CTRLDESCL0_5_BPP_32_ABGR8888, in lcdif_set_formats()
213 writel(CTRLDESCL0_5_BPP_32_ARGB8888, in lcdif_set_formats()
219 writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_VY2UY1, in lcdif_set_formats()
[all …]
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| /linux/arch/m68k/coldfire/ |
| H A D | m53xx.c | 317 writel(0x77777777, MCF_SCM_MPR); in scm_init()
321 writel(0, MCF_SCM_PACRA); in scm_init()
322 writel(0, MCF_SCM_PACRB); in scm_init()
323 writel(0, MCF_SCM_PACRC); in scm_init()
324 writel(0, MCF_SCM_PACRD); in scm_init()
325 writel(0, MCF_SCM_PACRE); in scm_init()
326 writel(0, MCF_SCM_PACRF); in scm_init()
329 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); in scm_init()
338 writel(0x10080000, MCF_FBCS1_CSAR); in fbcs_init()
340 writel(0x002A3780, MCF_FBCS1_CSCR); in fbcs_init()
[all …]
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| /linux/drivers/video/fbdev/geode/ |
| H A D | display_gx1.c | 86 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode()
93 writel(tcfg, par->dc_regs + DC_TIMING_CFG); in gx1_set_mode()
100 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
110 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode()
131 writel(0, par->dc_regs + DC_FB_ST_OFFSET); in gx1_set_mode()
134 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); in gx1_set_mode()
135 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, in gx1_set_mode()
162 writel(val, par->dc_regs + DC_H_TIMING_1); in gx1_set_mode()
164 writel(val, par->dc_regs + DC_H_TIMING_2); in gx1_set_mode()
[all …]
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| /linux/sound/soc/amd/ps/ |
| H A D | ps-common.c | 32 writel(ACP63_PGFSM_CNTL_POWER_ON_MASK, acp_base + ACP_PGFSM_CONTROL); in acp63_power_on()
42 writel(1, acp_base + ACP_SOFT_RESET); in acp63_reset()
50 writel(0, acp_base + ACP_SOFT_RESET); in acp63_reset()
57 writel(1, acp_base + ACP_EXTERNAL_INTR_ENB); in acp63_enable_interrupts()
58 writel(ACP_ERROR_IRQ, acp_base + ACP_EXTERNAL_INTR_CNTL); in acp63_enable_interrupts()
63 writel(ACP_EXT_INTR_STAT_CLEAR_MASK, acp_base + ACP_EXTERNAL_INTR_STAT); in acp63_disable_interrupts()
64 writel(0, acp_base + ACP_EXTERNAL_INTR_CNTL); in acp63_disable_interrupts()
65 writel(0, acp_base + ACP_EXTERNAL_INTR_ENB); in acp63_disable_interrupts()
77 writel(0x01, acp_base + ACP_CONTROL); in acp63_init()
84 writel(0, acp_base + ACP_ZSC_DSP_CTRL); in acp63_init()
[all …]
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