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Searched refs:write_sysreg_s (Results 1 – 25 of 42) sorted by relevance

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/linux/arch/arm64/include/asm/
H A Darm_dsu_pmu.h40 write_sysreg_s(val, CLUSTERPMCR_EL1); in __dsu_pmu_write_pmcr()
48 write_sysreg_s(val, CLUSTERPMOVSCLR_EL1); in __dsu_pmu_get_reset_overflow()
55 write_sysreg_s(counter, CLUSTERPMSELR_EL1); in __dsu_pmu_select_counter()
68 write_sysreg_s(val, CLUSTERPMXEVCNTR_EL1); in __dsu_pmu_write_counter()
75 write_sysreg_s(event, CLUSTERPMXEVTYPER_EL1); in __dsu_pmu_set_event()
86 write_sysreg_s(val, CLUSTERPMCCNTR_EL1); in __dsu_pmu_write_pmccntr()
92 write_sysreg_s(BIT(counter), CLUSTERPMCNTENCLR_EL1); in __dsu_pmu_disable_counter()
98 write_sysreg_s(BIT(counter), CLUSTERPMCNTENSET_EL1); in __dsu_pmu_enable_counter()
104 write_sysreg_s(BIT(counter), CLUSTERPMINTENSET_EL1); in __dsu_pmu_counter_interrupt_enable()
110 write_sysreg_s(BIT(counter), CLUSTERPMINTENCLR_EL1); in __dsu_pmu_counter_interrupt_disable()
H A Darch_gicv3.h20 #define write_gicreg(v, r) write_sysreg_s(v, SYS_ ## r)
31 write_sysreg_s(irq, SYS_ICC_DIR_EL1); in gic_write_dir()
92 write_sysreg_s(val, SYS_ICC_CTLR_EL1); in gic_write_ctlr()
103 write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1); in gic_write_grpen1()
109 write_sysreg_s(val, SYS_ICC_SGI1R_EL1); in gic_write_sgi1r()
119 write_sysreg_s(val, SYS_ICC_SRE_EL1); in gic_write_sre()
125 write_sysreg_s(val, SYS_ICC_BPR1_EL1); in gic_write_bpr1()
135 write_sysreg_s(val, SYS_ICC_PMR_EL1); in gic_write_pmr()
H A Dirqflags.h38 write_sysreg_s(GIC_PRIO_IRQON, SYS_ICC_PMR_EL1); in __pmr_local_irq_enable()
67 write_sysreg_s(GIC_PRIO_IRQOFF, SYS_ICC_PMR_EL1); in __pmr_local_irq_disable()
182 write_sysreg_s(flags, SYS_ICC_PMR_EL1); in __pmr_local_irq_restore()
H A Darm_pmuv3.h92 write_sysreg_s(val, SYS_PMICNTR_EL0); in write_pmicntr()
132 write_sysreg_s(val, SYS_PMICFILTR_EL0); in write_pmicfiltr()
157 write_sysreg_s(val, SYS_PMUACR_EL1); in write_pmuacr()
H A Dkvm_hyp.h28 #define write_sysreg_el0(v,r) write_sysreg_s(v, r##_EL02)
30 #define write_sysreg_el1(v,r) write_sysreg_s(v, r##_EL12)
32 #define write_sysreg_el2(v,r) write_sysreg_s(v, r##_EL1)
H A Dgcs.h126 write_sysreg_s(gcspr, SYS_GCSPR_EL0); in push_user_gcs()
155 write_sysreg_s(gcspr + sizeof(u64), SYS_GCSPR_EL0); in pop_user_gcs()
H A Dpointer_auth.h47 write_sysreg_s(__pki_v.lo, SYS_ ## k ## KEYLO_EL1); \
48 write_sysreg_s(__pki_v.hi, SYS_ ## k ## KEYHI_EL1); \
H A Dfpsimd.h228 write_sysreg_s(__new, (reg)); \
252 write_sysreg_s(tmp | val, SYS_ZCR_EL1); in write_vl()
258 write_sysreg_s(tmp | val, SYS_SMCR_EL1); in write_vl()
/linux/drivers/irqchip/
H A Dirq-gic-v5.c74 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR0_EL1); in gicv5_ppi_priority_init()
75 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR1_EL1); in gicv5_ppi_priority_init()
76 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR2_EL1); in gicv5_ppi_priority_init()
77 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR3_EL1); in gicv5_ppi_priority_init()
78 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR4_EL1); in gicv5_ppi_priority_init()
79 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR5_EL1); in gicv5_ppi_priority_init()
80 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR6_EL1); in gicv5_ppi_priority_init()
81 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR7_EL1); in gicv5_ppi_priority_init()
82 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR8_EL1); in gicv5_ppi_priority_init()
83 write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR9_EL1); in gicv5_ppi_priority_init()
[all …]
/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3.c104 write_sysreg_s(irq, SYS_ICC_EOIR1_EL1); in gicv3_write_eoir()
110 write_sysreg_s(irq, SYS_ICC_DIR_EL1); in gicv3_write_dir()
116 write_sysreg_s(mask, SYS_ICC_PMR_EL1); in gicv3_set_priority_mask()
128 write_sysreg_s(val, SYS_ICC_CTLR_EL1); in gicv3_set_eoi_split()
344 write_sysreg_s(read_sysreg_s(SYS_ICC_SRE_EL1) | ICC_SRE_EL1_SRE, in gicv3_cpu_init()
348 write_sysreg_s(ICC_PMR_DEF_PRIO, SYS_ICC_PMR_EL1); in gicv3_cpu_init()
351 write_sysreg_s(ICC_IGRPEN0_EL1_MASK, SYS_ICC_IGRPEN1_EL1); in gicv3_cpu_init()
353 write_sysreg_s(ICC_IGRPEN1_EL1_MASK, SYS_ICC_IGRPEN1_EL1); in gicv3_cpu_init()
/linux/drivers/soc/qcom/
H A Dkryo-l2-accessors.c29 write_sysreg_s(reg, L2CPUSRSELR_EL1); in kryo_l2_set_indirect_reg()
31 write_sysreg_s(val, L2CPUSRDR_EL1); in kryo_l2_set_indirect_reg()
50 write_sysreg_s(reg, L2CPUSRSELR_EL1); in kryo_l2_get_indirect_reg()
/linux/arch/arm64/kvm/hyp/include/hyp/
H A Dswitch.h207 write_sysreg_s(*vcpu_fgt(vcpu, reg), SYS_ ## reg); \
238 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
277 write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2); in __activate_traps_mpam()
283 write_sysreg_s(r, SYS_MPAM2_EL2); in __activate_traps_mpam()
291 write_sysreg_s(0, SYS_MPAM2_EL2); in __deactivate_traps_mpam()
294 write_sysreg_s(MPAMHCR_HOST_FLAGS, SYS_MPAMHCR_EL2); in __deactivate_traps_mpam()
327 write_sysreg_s(hcrx, SYS_HCRX_EL2); in __activate_traps_common()
345 write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2); in __deactivate_traps_common()
383 write_sysreg_s(vsesr, SYS_VSESR_EL2); in ___activate_traps()
459 write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2); in __hyp_sve_save_host()
[all …]
/linux/drivers/perf/
H A Darm_spe_pmu.c642 write_sysreg_s(base, SYS_PMBPTR_EL1); in arm_spe_perf_aux_output_begin()
645 write_sysreg_s(limit, SYS_PMBLIMITR_EL1); in arm_spe_perf_aux_output_begin()
666 write_sysreg_s(0, SYS_PMSCR_EL1); in arm_spe_pmu_disable_and_drain_local()
674 write_sysreg_s(0, SYS_PMBLIMITR_EL1); in arm_spe_pmu_disable_and_drain_local()
799 write_sysreg_s(0, SYS_PMBSR_EL1); in arm_spe_pmu_irq_handler()
894 write_sysreg_s(reg, SYS_PMSFCR_EL1); in arm_spe_pmu_start()
897 write_sysreg_s(reg, SYS_PMSEVFR_EL1); in arm_spe_pmu_start()
901 write_sysreg_s(reg, SYS_PMSNEVFR_EL1); in arm_spe_pmu_start()
906 write_sysreg_s(reg, SYS_PMSDSFR_EL1); in arm_spe_pmu_start()
910 write_sysreg_s(reg, SYS_PMSLATFR_EL1); in arm_spe_pmu_start()
[all …]
H A Darm_brbe.c266 write_sysreg_s(brbfcr, SYS_BRBFCR_EL1); in select_brbe_bank()
528 write_sysreg_s(brbcr & ~(BRBCR_ELx_ExBRE | BRBCR_ELx_E0BRE), SYS_BRBCR_EL12); in brbe_enable()
529 write_sysreg_s(brbcr, SYS_BRBCR_EL1); in brbe_enable()
534 write_sysreg_s(brbfcr, SYS_BRBFCR_EL1); in brbe_enable()
545 write_sysreg_s(BRBFCR_EL1_PAUSED, SYS_BRBFCR_EL1); in brbe_disable()
546 write_sysreg_s(0, SYS_BRBCR_EL1); in brbe_disable()
H A Dapple_m1_cpu_pmu.c233 write_sysreg_s(_val, SYS_IMP_APL_PMC## _idx ##_EL1); \
296 write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); in __m1_pmu_enable_counter()
331 write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); in __m1_pmu_enable_counter_interrupt()
456 write_sysreg_s(state, SYS_IMP_APL_PMCR0_EL1); in m1_pmu_handle_irq()
532 write_sysreg_s(val, SYS_IMP_APL_PMCR0_EL1); in __m1_pmu_set_mode()
/linux/arch/arm64/kernel/
H A Dmte.c191 write_sysreg_s(0, SYS_TFSR_EL1); in mte_check_tfsr_el1()
249 write_sysreg_s( in mte_update_gcr_excl()
277 write_sysreg_s(0, SYS_TFSRE0_EL1); in mte_thread_init_user()
327 write_sysreg_s(KERNEL_GCR_EL1, SYS_GCR_EL1); in mte_cpu_setup()
339 write_sysreg_s(rgsr, SYS_RGSR_EL1); in mte_cpu_setup()
342 write_sysreg_s(0, SYS_TFSR_EL1); in mte_cpu_setup()
343 write_sysreg_s(0, SYS_TFSRE0_EL1); in mte_cpu_setup()
H A Dprocess.c255 write_sysreg_s(0, SYS_TPIDR2_EL0); in tls_thread_flush()
281 write_sysreg_s(POR_EL0_INIT, SYS_POR_EL0); in flush_poe()
296 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); in flush_gcs()
297 write_sysreg_s(0, SYS_GCSPR_EL0); in flush_gcs()
539 write_sysreg_s(next->thread.tpidr2_el0, SYS_TPIDR2_EL0); in tls_thread_switch()
593 write_sysreg_s(next->thread.gcspr_el0, SYS_GCSPR_EL0); in gcs_thread_switch()
675 write_sysreg_s(next->thread.por_el0, SYS_POR_EL0); in permission_overlay_switch()
H A Dfpsimd.c407 write_sysreg_s(current->thread.svcr, SYS_SVCR); in task_fpsimd_load()
418 write_sysreg_s(current->thread.uw.fpmr, SYS_FPMR); in task_fpsimd_load()
728 write_sysreg_s(read_sysreg_s(SYS_SCTLR_EL1) | SCTLR_EL1_EnFPM_MASK, in cpu_enable_fpmr()
1096 write_sysreg_s(0, SYS_ZCR_EL1); in cpu_enable_sve()
1199 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK, in cpu_enable_sme()
1207 write_sysreg_s(0, SYS_SMCR_EL1); in cpu_enable_sme()
1220 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_EZT0_MASK, in cpu_enable_sme2()
1230 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK, in cpu_enable_fa64()
1288 write_sysreg_s(smcr, SYS_SMCR_EL1); in sme_suspend_exit()
1289 write_sysreg_s(0, SYS_SMPRI_EL1); in sme_suspend_exit()
/linux/drivers/hwtracing/coresight/
H A Dcoresight-trbe.h61 write_sysreg_s(trbsr, SYS_TRBSR_EL1); in clr_trbe_irq()
112 write_sysreg_s(addr, SYS_TRBPTR_EL1); in set_trbe_write_pointer()
138 write_sysreg_s(addr, SYS_TRBBASER_EL1); in set_trbe_base_pointer()
H A Dcoresight-trbe.c225 write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); in set_trbe_enabled()
244 write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); in set_trbe_disabled()
260 write_sysreg_s(0, SYS_TRBLIMITR_EL1); in trbe_reset_local()
263 write_sysreg_s(0, SYS_TRBPTR_EL1); in trbe_reset_local()
264 write_sysreg_s(0, SYS_TRBBASER_EL1); in trbe_reset_local()
265 write_sysreg_s(0, SYS_TRBSR_EL1); in trbe_reset_local()
597 write_sysreg_s(trbsr, SYS_TRBSR_EL1); in clr_trbe_status()
H A Dcoresight-self-hosted-trace.h20 write_sysreg_s(val, SYS_TRFCR_EL1); in write_trfcr()
/linux/tools/testing/selftests/kvm/arm64/
H A Dat.c22 write_sysreg_s(read_sysreg_s(SYS_##reg##_EL1), SYS_##reg##_EL12)
25 #define __at(op, addr) write_sysreg_s(addr, op)
/linux/drivers/edac/
H A Da72_edac.c108 write_sysreg_s(0, SYS_CPUMERRSR_EL1); in read_errors()
113 write_sysreg_s(0, SYS_L2MERRSR_EL1); in read_errors()
/linux/arch/arm64/kvm/
H A Dsys_regs.c261 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; in write_sr_to_cpu()
262 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; in write_sr_to_cpu()
263 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; in write_sr_to_cpu()
264 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; in write_sr_to_cpu()
265 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; in write_sr_to_cpu()
266 case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break; in write_sr_to_cpu()
267 case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break; in write_sr_to_cpu()
268 case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break; in write_sr_to_cpu()
269 case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break; in write_sr_to_cpu()
270 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; in write_sr_to_cpu()
[all …]
/linux/arch/arm64/mm/
H A Dgcs.c152 write_sysreg_s(gcscre0_el1, SYS_GCSCRE0_EL1); in gcs_set_el0_mode()
209 write_sysreg_s(task->thread.gcspr_el0, in arch_set_shadow_stack_status()

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